Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "ambric/am2000/am2045b"
| Line 40: | Line 40: | ||
| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
| − | | max memory = | + | | max memory = 4 GB |
| electrical = | | electrical = | ||
| Line 95: | Line 95: | ||
| bandwidth schan = | | bandwidth schan = | ||
| bandwidth dchan = | | bandwidth dchan = | ||
| − | | max memory = | + | | max memory = 4 GB |
}} | }} | ||
Revision as of 17:06, 24 June 2016
Template:mpu Am2045B was Ambric's flagship MPPA introduced in late 2007. This model was made of roughly 45 Brics arranged as a grid of 5x9, making up a total of 336 32-bit RICS-like cores operating asynchronously at 1-350 MHz. This was an enhanced version of the original which featured a higher bandwidth network on a chip (Ambric claimed up to 40 percent improvement), operated at higher frequency, and provided up to 1.2 trillion operations per seconds theoretical peak computation. This model also had lower power consumption over the original.
Architecture
- Main article: Am2000 § Architecture
The Am2045B is made of 45 homogeneous 'Brics' laid out in a grid to form 336 cores.
General layout:
- 16x Brics
Memory controller
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
| Max memory | 4 GB |
Expansions
- PCIe
- JTAG
- 128x GPIO @ 100 MHz
- serial flash