Semiconductor & Computer Engineering
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| − | '''KiloCore''' is a prototype [[microprocessor]] containing 1,000 cores developed by the VLSI Computation Laboratory (VCL) at UC Davis. The chip, which was manufactured on [[IBM]]'s [[32 nm process]] PD-SOI technology, is said to have a maximum computation rate of 1.78 trillion instructions per second. This chip was presented at the 2016 Symposia on VLSI Technology and Circuits on June 17, 2016. | + | '''KiloCore''' is a prototype {{arch|16}} [[microprocessor]] containing 1,000 cores developed by the VLSI Computation Laboratory (VCL) at UC Davis. The chip, which was manufactured on [[IBM]]'s [[32 nm process]] PD-SOI technology, is said to have a maximum computation rate of 1.78 trillion instructions per second. This chip was presented at the 2016 Symposia on VLSI Technology and Circuits on June 17, 2016. |
| + | |||
| + | == Architecture == | ||
| + | The chip is arranged as an array of 992 cores arranged as a grid 32 by 31. 8 Additional cores are found along with 12 memory modules of 64 KB SRAM ea (for a total of 768 KB). Communication between cores is done via a [[circuit-switched network]] and a very-small-area packet router. | ||
| + | |||
| + | === Cores === | ||
| + | Each core is an independent processing unit capable of issuing one instruction [[in-order]] per cycle. Instructions may come from the local instruction memory or they may be fetched from one of the independent memory module. Likewise data may come from the data memroy or from the independent memory module. | ||
| + | |||
| + | Each core contains 128x40-bit local instruction memory. Data memory is also stored in each as 2 banks of 128x16-bit each (for a total of 256x16-bit). The core also has three data address generators, two 32x16 input FIFO buffers, a 16-bit fixed-poit data path. | ||
| + | |||
| + | === Memory Module === | ||
| + | Each memory module contains 64 KB of SRAM and has an area of 0.164 mm². The module also contains two 32x16-bit FIFO buffers. | ||
| + | |||
| + | == ISA == | ||
| + | Each core supports 72 general instructions supporting [[signed]] and [[unsigned]] operations. The processor operates on {{arch|16}} data [[word size]] with the exception of the multiply-accumulator which has a 40-bit output. Larger word size operations such as {{arch|32}} may be emulated via software. | ||
| + | |||
| + | == Cache == | ||
| + | * Per core | ||
| + | ** 640 bytes (128x40-bit) local instruction memory | ||
| + | ** 512 bytes (256x16-bit) local data memory | ||
| + | * 768 KB SRAM on-die | ||
| + | ** 12 shared SRAM memory modules, 64 KB each | ||
Revision as of 03:18, 20 June 2016
Template:mpu KiloCore is a prototype 16-bit microprocessor containing 1,000 cores developed by the VLSI Computation Laboratory (VCL) at UC Davis. The chip, which was manufactured on IBM's 32 nm process PD-SOI technology, is said to have a maximum computation rate of 1.78 trillion instructions per second. This chip was presented at the 2016 Symposia on VLSI Technology and Circuits on June 17, 2016.
Contents
Architecture
The chip is arranged as an array of 992 cores arranged as a grid 32 by 31. 8 Additional cores are found along with 12 memory modules of 64 KB SRAM ea (for a total of 768 KB). Communication between cores is done via a circuit-switched network and a very-small-area packet router.
Cores
Each core is an independent processing unit capable of issuing one instruction in-order per cycle. Instructions may come from the local instruction memory or they may be fetched from one of the independent memory module. Likewise data may come from the data memroy or from the independent memory module.
Each core contains 128x40-bit local instruction memory. Data memory is also stored in each as 2 banks of 128x16-bit each (for a total of 256x16-bit). The core also has three data address generators, two 32x16 input FIFO buffers, a 16-bit fixed-poit data path.
Memory Module
Each memory module contains 64 KB of SRAM and has an area of 0.164 mm². The module also contains two 32x16-bit FIFO buffers.
ISA
Each core supports 72 general instructions supporting signed and unsigned operations. The processor operates on 16-bit data word size with the exception of the multiply-accumulator which has a 40-bit output. Larger word size operations such as 32-bit may be emulated via software.
Cache
- Per core
- 640 bytes (128x40-bit) local instruction memory
- 512 bytes (256x16-bit) local data memory
- 768 KB SRAM on-die
- 12 shared SRAM memory modules, 64 KB each