From WikiChip
Difference between revisions of "intel/80486/486dx-33"
(rm dup params) |
(→Cache) |
||
Line 87: | Line 87: | ||
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1 cache=8 | + | |l1 cache=8 KiB |
− | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
− | |l1 extra=(unified, write-through policy ) | + | |l1 extra=(unified, write-through policy) |
}} | }} | ||
Revision as of 21:55, 20 September 2016
Template:mpu i486DX-33 was a fourth-generation x86 microprocessor introduced by Intel in 1990. This chip, which is based on the 80486 microarchitecture, operated at 33 MHz. This chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
Gallery
See also
Facts about "i486DX-33 - Intel"
l1$ description | 4-way set associative + |
l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |