Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/am486/am486sx2-66"
(→Cache) |
|||
| Line 82: | Line 82: | ||
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
|l1 extra=(unified, write-through policy) | |l1 extra=(unified, write-through policy) | ||
Revision as of 22:47, 20 September 2016
Template:mpu Am486SX2-66 was an 80486-compatible microprocessor introduced by AMD in early 1994. This processor has a clock multiplier of 2 with a core frequency of 66 MHz and a bus frequency of 33 MHz. As with the rest of the 486SX series, this MPU does not have a functional FPU on-die.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
See also
Facts about "Am486SX2-66 - AMD"
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |