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Difference between revisions of "amd/am486/am486dx2-50"
< amd‎ | am486

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{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}
 
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}
 
{{cache info
 
{{cache info
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|l1 cache=8 KB
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|l1 cache=8 KiB
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|l1 break=1x8 KB
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|l1 break=1x8 KiB
 
|l1 desc=4-way set associative
 
|l1 desc=4-way set associative
 
|l1 extra=(unified, write-through policy)
 
|l1 extra=(unified, write-through policy)

Revision as of 21:42, 20 September 2016

Template:mpu Am486DX2-50 was an 80486-compatible microprocessor introduced by AMD in 1993. This processor had a clock multiplier of 2 having base frequency of 50 MHz with a FSB frequency of 25 MHz.

Cache

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 8 KiB
8,192 B
0.00781 MiB
1x8 KiB 4-way set associative (unified, write-through policy)

Graphics

This chip had no integrated graphics processing unit.

See also

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l1$ description4-way set associative +
l1$ size8 KiB (8,192 B, 0.00781 MiB) +