Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx4-100nv8t"
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| − | '''Am486DX2-100NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of {{\\|Am486DX4-100V8T}} (and earlier {{\\|Am486DX4-100}}) that no longer included Intel's ICE microcode. | + | '''Am486DX2-100NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of {{\\|Am486DX4-100V8T}} (and earlier {{\\|Am486DX4-100}}) that {{amd|Am486#Larger Cache & Post-lawsuit|no longer included Intel's ICE microcode}}. |
== Cache == | == Cache == | ||
Revision as of 03:35, 17 May 2016
Template:mpu Am486DX2-100NV8T was an 80486-compatible microprocessor introduced by AMD in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of Am486DX4-100V8T (and earlier Am486DX4-100) that no longer included Intel's ICE microcode.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Documents
Gallery
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Die Shot
