Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx2-50"
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Revision as of 03:26, 17 May 2016
Template:mpu Am486DX2-50 was an 80486-compatible microprocessor introduced by AMD in 1993. This processor had a clock multiplier of 2 having base frequency of 50 MHz with a FSB frequency of 25 MHz.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
See also
Facts about "Am486DX2-50 - AMD"
| base frequency | 50 MHz (0.05 GHz, 50,000 kHz) + |
| bus rate | 25 MT/s (0.025 GT/s, 25,000 kT/s) + |
| bus speed | 25 MHz (0.025 GHz, 25,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 2 + |
| core count | 1 + |
| core name | 486DX2 + |
| core voltage | 5 V (50 dV, 500 cV, 5,000 mV) + |
| designer | AMD + |
| family | Am486 + |
| first announced | April 1993 + |
| first launched | June 1993 + |
| full page name | amd/am486/am486dx2-50 + |
| instance of | microprocessor + |
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| ldate | June 1993 + |
| manufacturer | AMD + |
| market segment | Desktop + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | 80486 + |
| min operating temperature | 0 °C + |
| model number | Am486DX2-50 + |
| name | Am486DX2-50 + |
| part number | A80486DX2-50 + |
| process | 700 nm (0.7 μm, 7.0e-4 mm) + and 500 nm (0.5 μm, 5.0e-4 mm) + |
| series | Am486DX2 + |
| smp max ways | 1 + |
| technology | CMOS + |
| transistor count | 1,200,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |