Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx4-100v8t"
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| − | '''Am486DX2-100V8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1994. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model was simply renamed from {{\\|Am486DX4-100}} to differentiate it from the {{\\|Am486DX4-100V16B}} which is a similar model with a Write-Back cache policy and | + | '''Am486DX2-100V8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1994. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model was simply renamed from {{\\|Am486DX4-100}} to differentiate it from the {{\\|Am486DX4-100V16B}} which is a similar model with a Write-Back cache policy and double the cache size. |
== Cache == | == Cache == | ||
Revision as of 20:16, 15 May 2016
Template:mpu Am486DX2-100V8T was an 80486-compatible microprocessor introduced by AMD in 1994. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model was simply renamed from Am486DX4-100 to differentiate it from the Am486DX4-100V16B which is a similar model with a Write-Back cache policy and double the cache size.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.