Semiconductor & Computer Engineering
(→Cache) |
(rm dup params) |
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| Line 44: | Line 44: | ||
| s-spec 13 = SX906 | | s-spec 13 = SX906 | ||
| s-spec es = | | s-spec es = | ||
| − | | s-spec qs | + | | s-spec qs 2 = Q0746 |
| − | | s-spec qs | + | | s-spec qs 3 = Q0747 |
| − | | s-spec qs | + | | s-spec qs 4 = Q860 |
| cpuid = 480 | | cpuid = 480 | ||
| − | | cpuid | + | | cpuid 2 = 483 |
| microarch = 80486 | | microarch = 80486 | ||
Revision as of 02:22, 21 May 2016
Template:mpu i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.
Contents
Cache
- Main article: 80486 § Cache
The i486dx4-100 was offered with two cache policies. Models that came with a write-back cache were marked by an "&EW" identifier. Models that came with a write-through policy were marked by "&E".
| Cache Info [Edit Values] | ||
| L1$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 4-way set associative (unified, write-through/write-back policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
Gallery
A80486DX4100, S-Spec SK096
A80486DX4100, S-Spec SK096
A80486DX4100, S-Spec SK096
A80486DX4100, S-Spec SK051
A80486DX4100, S-Spec SK051
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