Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486dx2-50"
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| Line 37: | Line 37: | ||
| s-spec 9 = SX768 | | s-spec 9 = SX768 | ||
| s-spec 10 = SX808 | | s-spec 10 = SX808 | ||
| − | | s-spec 11 = SX912 | + | | s-spec 11 = SX825 |
| − | | s-spec | + | | s-spec 12 = SX912 |
| + | | s-spec 13 = SX920 | ||
| + | | s-spec 14 = SX954 | ||
| s-spec es = | | s-spec es = | ||
| s-spec qs = Q0382 | | s-spec qs = Q0382 | ||
Revision as of 17:40, 11 May 2016
Template:mpu i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy ) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
Gallery
A80486DX2-50, S-Spec SX808
A80486DX2-50, S-Spec SX641
SB80486DX2-50, S-Spec SX920
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