Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486dx2-50"
| Line 28: | Line 28: | ||
| bus rate = 25 MT/s | | bus rate = 25 MT/s | ||
| clock multiplier = 2 | | clock multiplier = 2 | ||
| − | | s-spec = | + | | s-spec = SX626 |
| + | | s-spec 2 = SX627 | ||
| + | | s-spec 3 = SX641 | ||
| + | | s-spec 4 = SX721 | ||
| + | | s-spec 5 = SX738 | ||
| + | | s-spec 6 = SX749 | ||
| + | | s-spec 7 = SX760 | ||
| + | | s-spec 8 = SX761 | ||
| + | | s-spec 9 = SX768 | ||
| + | | s-spec 10 = SX808 | ||
| + | | s-spec 11 = SX912 | ||
| + | | s-spec 12 = SX954 | ||
| s-spec es = | | s-spec es = | ||
| − | | s-spec qs = | + | | s-spec qs = Q0382 |
| − | | s-spec qs 2 = | + | | s-spec qs 2 = Q0424 |
| − | | cpuid = | + | | cpuid = 432 |
| + | | cpuid 2 = 433 | ||
| + | | cpuid 3 = 435 | ||
| + | | cpuid 4 = 436 | ||
| microarch = 80486 | | microarch = 80486 | ||
| Line 52: | Line 66: | ||
| electrical = Yes | | electrical = Yes | ||
| − | | power = 3. | + | | power = 3.88 W |
| v core = 5 V | | v core = 5 V | ||
| v core tolerance = 5% | | v core tolerance = 5% | ||
Revision as of 15:33, 11 May 2016
Template:mpu i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy ) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
See also
Facts about "i486DX2-50 - Intel"
| base frequency | 50 MHz (0.05 GHz, 50,000 kHz) + |
| bus rate | 25 MT/s (0.025 GT/s, 25,000 kT/s) + |
| bus speed | 25 MHz (0.025 GHz, 25,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 2 + |
| core count | 1 + |
| core name | 486DX2 + |
| core voltage | 5 V (50 dV, 500 cV, 5,000 mV) + |
| core voltage tolerance | 5% + |
| cpuid | 432 +, 433 +, 435 + and 436 + |
| designer | Intel + |
| family | 80486 + |
| first launched | March 3, 1992 + |
| full page name | intel/80486/486dx2-50 + |
| instance of | microprocessor + |
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| ldate | March 3, 1992 + |
| main image | .JPG) + |
| main image caption | SB80486DX2-50 + |
| manufacturer | Intel + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | 80486 + |
| min operating temperature | 0 °C + |
| model number | i486DX2-50 + |
| name | Intel i486DX2-50 + |
| part number | A80486DX2-50 +, MA80486DX2-50 +, MQ80486DX2-50 +, TQ80486DX250 + and SB80486DX2-50 + |
| power dissipation | 3.88 W (3,880 mW, 0.0052 hp, 0.00388 kW) + |
| process | 1,000 nm (1 μm, 0.001 mm) + and 800 nm (0.8 μm, 8.0e-4 mm) + |
| s-spec | SX626 +, SX627 +, SX641 +, SX721 +, SX738 +, SX749 +, SX760 +, SX761 +, SX768 +, SX808 +, SX825 +, SX912 +, SX920 + and SX954 + |
| s-spec (qs) | Q0382 + and Q0424 + |
| series | 486DX2 + |
| smp max ways | 1 + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |
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