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Difference between revisions of "intel/80486/486sx-33"
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| core stepping = | | core stepping = | ||
| process = 1 µm | | process = 1 µm | ||
| − | | transistors = 900,000 | + | | process 2 = 800 nm |
| + | | transistors = 1,185,000 | ||
| + | | transistors 2 = 900,000 | ||
| technology = CMOS | | technology = CMOS | ||
| die size = | | die size = | ||
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| socket 3 = Socket 3 | | socket 3 = Socket 3 | ||
}} | }} | ||
| + | '''i486SX-33''' was a fourth-generation [[x86]] [[microprocessor]] introduced by [[Intel]] in 1991. This chip, which is based on the {{intel|microarchitectures/80486|80486 microarchitecture}}, operated at 33 MHz. In contrast to the i486DX chips, the i486SX line had no functional [[FPU]] on-die. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
| + | {{cache info | ||
| + | |l1 cache=8 KB | ||
| + | |l1 break=1x8 KB | ||
| + | |l1 desc=4-way set associative | ||
| + | |l1 extra=(unified, write-through policy) | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This chip had no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | * {{intel|System Management Mode}} (SMM) | ||
| + | |||
| + | == See also == | ||
| + | * {{intel|80486|80486 family}} | ||
Revision as of 14:29, 11 May 2016
Template:mpu i486SX-33 was a fourth-generation x86 microprocessor introduced by Intel in 1991. This chip, which is based on the 80486 microarchitecture, operated at 33 MHz. In contrast to the i486DX chips, the i486SX line had no functional FPU on-die.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)