Semiconductor & Computer Engineering
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Difference between revisions of "intel/mobile pentium ii/233"
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== Cache == | == Cache == | ||
| − | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 | + | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 § Cache}} |
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=16 | + | |l1d cache=16 KiB |
| − | |l1d break=1x16 | + | |l1d break=1x16 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=512 | + | |l2 cache=512 KiB |
| − | |l2 break=1x512 | + | |l2 break=1x512 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(separate die, same package) | |l2 extra=(separate die, same package) | ||
Revision as of 23:57, 20 September 2016
Template:mpu The Mobile Pentium II 233 was a 32-bit x86 microprocessor, the first of the Mobile Pentium II family. This processor operated at 233 MHz and had a TDP of 9 Watts. This chip was manufactured in 250 nm process and included a larger 512 KB of L2$ on package, but on a separate die.
Contents
Cache
- Main article: P6 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
1x512 KiB 4-way set associative (separate die, same package) |
Graphics
This processor has no integrated graphics processing unit.
Memory controller
This processor has no integrated memory controller.
Features
Facts about "Mobile Pentium II 233 - Intel"
| l1d$ description | 4-way set associative + |
| l1i$ description | 4-way set associative + |
| l2$ description | 4-way set associative + |