From WikiChip
Difference between revisions of "intel/xeon d/d-1540"
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| socket type = BGA | | socket type = BGA | ||
}} | }} | ||
+ | The '''{{intel|Xeon D}}-1540''' is a {{arch|64}} octa-core [[x86-64]] microserver SoC that was introduced by [[Intel]] in March of 2015. The D-1540 operates at 2 GHz with a turbo frequency of 2.6 GHz. This chip, which is based on the [[intel/microarchitectures/broadwell|Broadwell]] [[microarchitecture]] and manufactured in [[14 nm process]], has a TDP of 45 W and can support up to 128 GB of RAM (DDR4). | ||
== Cache == | == Cache == | ||
Line 80: | Line 81: | ||
|l2 extra=(per core) | |l2 extra=(per core) | ||
|l3 cache=12 MB | |l3 cache=12 MB | ||
+ | |l3 break=8x1.5 MB | ||
|l3 desc= | |l3 desc= | ||
− | |l3 extra=( | + | |l3 extra=(per core) |
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This SoC has no integrated graphics processing unit. | ||
+ | |||
+ | == Memory controller == | ||
+ | {{integrated memory controller | ||
+ | | type = DDR4-1600 | ||
+ | | type 2 = DDR4-1867 | ||
+ | | type 3 = DDR4-2133 | ||
+ | | controllers = 1 | ||
+ | | channels = 2 | ||
+ | | ecc support = Yes | ||
+ | | max bandwidth = | ||
+ | | bandwidth schan = | ||
+ | | bandwidth dchan = | ||
+ | | max memory = 128 GB | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{mpu expansions | ||
+ | | pcie revision = 2.0 | ||
+ | | pcie revision 2 = 3.0 | ||
+ | | pcie lanes = 8 | ||
+ | | pcie lanes 2 = 32 | ||
+ | | pcie config = x4 | ||
+ | | pcie config 1 = x8 | ||
+ | | pcie config 2 = x16 | ||
+ | | usb revision = 2.0 | ||
+ | | usb revision 2 = 3.0 | ||
+ | | usb ports = 8 | ||
+ | | sata ports = 6 | ||
+ | | integrated lan = Yes | ||
+ | | uart = Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{soc networking | ||
+ | | SFI interface = No | ||
+ | | KR interface = No | ||
+ | | KR4 Interface = No | ||
+ | | KX Interface = No | ||
+ | | KX4 Interface = No | ||
+ | | 10Base-T = No | ||
+ | | 100Base-T = No | ||
+ | | 1000Base-T = No | ||
+ | | 10GBase-T = Yes | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{mpu features | ||
+ | | em64t = Yes | ||
+ | | nx = Yes | ||
+ | | txt = Yes | ||
+ | | tsx = Yes | ||
+ | | ht = Yes | ||
+ | | tbt2 = Yes | ||
+ | | bpt = | ||
+ | | vt-x = Yes | ||
+ | | vt-d = Yes | ||
+ | | mmx = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = Yes | ||
+ | | sse3 = Yes | ||
+ | | ssse3 = Yes | ||
+ | | sse4 = Yes | ||
+ | | sse4.1 = Yes | ||
+ | | sse4.2 = Yes | ||
+ | | aes = Yes | ||
+ | | avx = Yes | ||
+ | | avx2 = Yes | ||
+ | | bmi = Yes | ||
+ | | bmi1 = Yes | ||
+ | | bmi2 = Yes | ||
+ | | f16c = Yes | ||
+ | | fma3 = Yes | ||
+ | | sgx = | ||
+ | | eist = Yes | ||
+ | | secure key = Yes | ||
+ | | os guard = Yes | ||
}} | }} |
Revision as of 23:54, 11 April 2016
Template:mpu The Xeon D-1540 is a 64-bit octa-core x86-64 microserver SoC that was introduced by Intel in March of 2015. The D-1540 operates at 2 GHz with a turbo frequency of 2.6 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR4).
Cache
- Main article: Broadwell's Cache
Cache Info [Edit Values] | ||
L1I$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
8x32 KB 8-way set associative (per core) |
L1D$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
8x32 KB 8-way set associative (per core) |
L2$ | 2 MB "MB" is not declared as a valid unit of measurement for this property. |
8x256 KB 8-way set associative (per core) |
L3$ | 12 MB "MB" is not declared as a valid unit of measurement for this property. |
8x1.5 MB (per core) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR4-1600, DDR4-1867, DDR4-2133 |
Controllers | 1 |
Channels | 2 |
ECC Support | Yes |
Max memory | 128 GB |
Expansions
Networking
Networking | |
SFI interface | No |
KR interface | No |
10Base-T | No |
100Base-T | No |
1000Base-T | No |
10GBase-T | Yes |
Features
Facts about "Xeon D-1540 - Intel"
l1d$ description | 8-way set associative + |
l1i$ description | 8-way set associative + |
l2$ description | 8-way set associative + |