Revision as of 07:31, 8 April 2016

Code

{{microarchitecture
| name          = 
| manufacturer  = 
| introduction  = 
| phase-out     =
| process       = 
| cores         = 
| cores 2       = 
| cores N       = 

| pipeline      = <!-- yes for following options -->
| type          = <!-- e.g. "Superscalar" -->
| OoOE          = <!-- Yes or No only -->
| isa           =
| isa 2         =
| isa N         =
| stages        = 
| ipc           = 

| inst          = <!-- yes for instructions options -->
| feature       = 
| extension     = 

| cache         = <!-- yes for cache info -->
| l1i           =
| l1i per       =
| l1i desc      =
| l1d           = 
| l1d per       = 
| l1d desc      =
| l2            = 
| l2  per       = 
| l2  desc      = 

| core names       = <!-- Yes if specify -->
| core name        =
| core name 2      =
| core name N      =

| succession       = <!-- yes for succession info -->
| predecessor      =
| predecessor link =
| successor        =
| successor link   =
}}