Difference between revisions of "intel/celeron/3955u"

From WikiChip

< intel‎ | celeron

Revision as of 09:36, 2 May 2016

Template:mpu The Intel Celeron 3955U is a dual-core 64-bit mobile microprocessor released by Intel in the third quarter of 2015. The 3955U is designed to replace the Broadwell-based celeron. Manufactured using 14nm process, the Skylake-based 3955U Celeron processor can be configured to run at down to 10 Watt TDP. This processor, just like its predecessor lack support for any of Intel's advanced technologies such as hyper-threading, trusted execution, transactional synchronization extensions (TSX), and turbo-boost.

1 Cache
2 Graphics
3 Memory controller
4 Expansions
5 Features

Cache

Cache Info [Edit Values]
L1I$	64 KB "KB" is not declared as a valid unit of measurement for this property.	2x32 KB
L1D$	64 KB "KB" is not declared as a valid unit of measurement for this property.	2x32 KB
L2$	512 KB "KB" is not declared as a valid unit of measurement for this property.	2x256 KB 4-way set associative
L3$	2 MB "MB" is not declared as a valid unit of measurement for this property.

Graphics

Integrated Graphic Information
GPU	Intel HD Graphics 510
Displays	3
Frequency	300 MHz 0.3 GHz 300,000 KHz
Max frequency	900 MHz 0.9 GHz 900,000 KHz
Max memory	1700 MB "MB" is not declared as a valid unit of measurement for this property.
Output	DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX	12
OpenGL	4.4
Max HDMI Res	4096x2304 @24 Hz
Max DP Res	4096x2304 @60 Hz
Max eDP Res	4096x2304 @60 Hz

Memory controller

Integrated Memory Controller
Type	DDR4-1866, DDR4-2133, LPDDR3-1600, LPDDR3-1866
Controllers	1
Channels	2
Max bandwidth	34,100 MB/s
Max memory	32,768 MB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/3955u&oldid=17694"

Facts about "Celeron 3955U - Intel"

RDF feed

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Celeron 3955U - Intel#package + and Celeron 3955U - Intel#io +
base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
bus rate	4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus type	OPI +
clock multiplier	20 +
core count	2 +
core family	6 +
core model	78 +
core name	Skylake U +
core stepping	D1 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
designer	Intel +
device id	0x1906 +
die area	98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) +
die count	2 +
die length	10.3 mm (1.03 cm, 0.406 in, 10,300 µm) +
die width	9.57 mm (0.957 cm, 0.377 in, 9,570 µm) +
family	Celeron +
first announced	August 15, 2015 +
first launched	December 27, 2015 +
full page name	intel/celeron/3955u +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Secure Key Technology +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology +, Identity Protection Technology +, Extended Page Tables + and Software Guard Extensions +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel identity protection technology support	true +
has intel my wifi technology support	true +
has intel secure key technology	true +
has intel smart response technology support	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics 510 +
integrated gpu base frequency	300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	12 +
integrated gpu max frequency	900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory	32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	December 27, 2015 +
main image	+
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	12 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Skylake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	3955U +
name	Celeron 3955U +
package	FCBGA-1356 +
part number	FJ8066201931006 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) +
s-spec	SR2EW +
series	3000 +
smp max ways	1 +
supported memory type	DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 +
tdp	15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
tdp down	10 W (10,000 mW, 0.0134 hp, 0.01 kW) +
technology	CMOS +
thread count	2 +
transistor count	1,750,000,000 +
word size	64 bit (8 octets, 16 nibbles) +
x86/has software guard extensions	true +

@@ Line 31: / Line 31: @@
 | microarch          = Skylake
 | platform           =
-| core name          = Skylake-U
+| core name          = Skylake U
 | core stepping      =
 | process            = 14 nm

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas