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Difference between revisions of "intel/crystal well"
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{{intel title|Crystal Well}}
 
{{intel title|Crystal Well}}
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'''Crystal Well''' is the codename for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the [[Iris Pro]]-equipped Intel [[Haswell]] microprocessors. The eDRAM silicon die is separate from the main [[Haswell]] die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013.
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'''[[codename::Crystal Well]]''' is the codename for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris Pro]]-equipped Intel [[Haswell]] microprocessors. The eDRAM silicon die is separate from the main [[Haswell]] die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013.
  
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== Details ==
 
Crystal Well is a true 128MB [[L4 Cache|L4$]] which could be utilized by the core itself, not just by the [[Iris Pro]]'s [[framebuffer]]. I.E. L3$ values that gets evicted go into L4$. The L4$ caches serve GPU and CPU memory accesses; memory is partitioned between the two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
 
Crystal Well is a true 128MB [[L4 Cache|L4$]] which could be utilized by the core itself, not just by the [[Iris Pro]]'s [[framebuffer]]. I.E. L3$ values that gets evicted go into L4$. The L4$ caches serve GPU and CPU memory accesses; memory is partitioned between the two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
  
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== Processors ==
 
== Processors ==
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{| class="wikitable sortable"
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<!-- NOTE:
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|-
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          This table is generated automatically from the data in the actual articles.
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! colspan="9" style="background:#D6D6FF;" | Crystal Well Processors
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
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          created and tagged with [[has feature::Crystal Well]] property.
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! Family !! Number !! Launch Date !! Cores !! Threads !! Clock !! Lithography !! TDP !! Die Size
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-->
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<table class="wikitable sortable">
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4950HQ|4950HQ]]   ||Q3 2013  ||4 ||8 ||2.4 GHz  ||22 nm ||47 W || 37.5mm x 32mm
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<tr><th colspan="8" style="background:#D6D6FF;">Crystal Well Processors</th></tr>
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|-
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<tr><th>Model</th><th>Family</th><th>Microarchitecture</th><th>Launched</th><th>Cores</th><th>Threads</th><th>Frequency</th><th>Process</th></tr>
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4850HQ|4850HQ]]  ||Q3 2013  ||4 ||8 ||2.3 GHz  ||22 nm ||47 W || 37.5mm x 32mm
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{{#ask:
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|-
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    [[Category:microprocessor models by intel]]
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4750HQ|4750HQ]]  ||Q3 2013  ||4 ||8 ||2 GHz ||22 nm ||47 W || 37.5mm x 32mm
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    [[has feature::Crystal Well]]
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|-
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  |?full page name
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4960HQ|4960HQ]]  ||Q4 2013  ||4 ||8 ||2.6 GHz  ||22 nm ||47 W || 37.5mm x 32mm
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|?model number
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|-
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  |?microprocessor family
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4770R|4770R]]    ||Q2 2013  ||4 ||8 ||3.2 GHz  ||22 nm ||65 W || 37.5mm x 32mm
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|?microarchitecture
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|-
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  |?first launched
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|[[Intel Core i5|Core i5]] || [[Intel Core i5-4570R|4570R]] || Q2 2013 || 4 || 8 ||2.7 GHz ||22 nm ||65 W || 37.5mm x 32mm
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|?core count
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|-
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  |?thread count
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|[[Intel Core i5|Core i5]] || [[Intel Core i5-4670R|4670R]] || Q2 2013 || 4 || 8 ||3 GHz  ||22 nm ||65 W  || 37.5mm x 32mm
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|?base frequency
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|}
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  |?process
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  |format=template
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|template=proc table 1
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|mainlabel=-
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}}
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</table>
  
 
== External links ==
 
== External links ==

Revision as of 16:19, 28 December 2015

Crystal Well is the codename for the L4 cache, a discrete eDRAM silicon die, which is featured in the high-end Iris Pro-equipped Intel Haswell microprocessors. The eDRAM silicon die is separate from the main Haswell die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013.

Details

Crystal Well is a true 128MB L4$ which could be utilized by the core itself, not just by the Iris Pro's framebuffer. I.E. L3$ values that gets evicted go into L4$. The L4$ caches serve GPU and CPU memory accesses; memory is partitioned between the two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.

Intel has not disclosed many technical specs regarding how the Crystal Well die communicates with the main die. Intel has stated that the cache is capable of delivering 100GB/s bandwidth (50GB/s in each direction).

Processors

Crystal Well Processors
ModelFamilyMicroarchitectureLaunchedCoresThreadsFrequencyProcess
i5-4570RCore i5Haswell
i5-4670RCore i5Haswell
i7-4750HQCore i7Haswell
i7-4760HQCore i7Haswell
i7-4770HQCore i7Haswell
i7-4770RCore i7Haswell
i7-4850EQCore i7Haswell
i7-4850HQCore i7Haswell
i7-4860EQCore i7Haswell
i7-4860HQCore i7Haswell
i7-4870HQCore i7Haswell
i7-4950HQCore i7Haswell
i7-4960HQCore i7Haswell
i7-4980HQCore i7Haswell
E3-1284L v3Xeon E3Haswell

External links

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