Semiconductor & Computer Engineering
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'''Self-Aligned Contact''' ('''SAC''') is a semiconductor process flow technique that adds a protective dielectric layer over the transistor gate in order to prevent contact-to-gate shorts. SAC is [[scaling booster|used to enable aggressive scaling]] of the contacted poly pitch while minimizing [[yield]] loss due to misalignment and partial overlaps of the contacts over the gate. | '''Self-Aligned Contact''' ('''SAC''') is a semiconductor process flow technique that adds a protective dielectric layer over the transistor gate in order to prevent contact-to-gate shorts. SAC is [[scaling booster|used to enable aggressive scaling]] of the contacted poly pitch while minimizing [[yield]] loss due to misalignment and partial overlaps of the contacts over the gate. | ||
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== Industry == | == Industry == | ||
Revision as of 20:59, 17 March 2025
Self-Aligned Contact (SAC) is a semiconductor process flow technique that adds a protective dielectric layer over the transistor gate in order to prevent contact-to-gate shorts. SAC is used to enable aggressive scaling of the contacted poly pitch while minimizing yield loss due to misalignment and partial overlaps of the contacts over the gate.
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We’ve been analyzing sites in your sector, and wikichip.org stood out. However, there are a few areas we believe should use some attention to optimize your SEO.
We’re offering a complimentary SEO report with several practical steps you can act on right away.
Let me know if this is the right person to send it!
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Contents
[hide]Industry
Memory
SAC has been used for over a decade in memory prior to its introduction in logic in both Flash and DRAM.
Intel
Intel introduced SAC along with the first high-volume FinFET process at their 22 nm process node. Three new steps were introduced. The flow is as follow.
- Intel's standard process is used to form the gate metal
- The gate electrode is recessed
- The recessed area is filled with silicon nitride etch stop & polish
- Capping oxide
- Contact patterning
Following their standard process for forming the metal gate and after it has been planarized, the gate is recessed back. The silicon nitride etch stop is then deposited and planarized forming an isolation layer followed by a capping oxide layer. Finally, the contact etching can then follow, allowing contacts to land directly on the gate without causing a shot.
The TEM below, taken by Intel, shows contacts that were intentionally overlaid on the gate, demonstrating the contacts can land on or near the gate due to misalignment and still work as desired.
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Without SAC, for their 22 nm process, Intel reports a contact landing misalignment of roughly ± 5 nm. A misalignment of up to ± 10nm drops the yield of passing dies down to close to 80% with anything higher drops the yield sharply. With SAC, no yield loss is observed due to contact misalignment which extends the tolerance to as much as ± 25 nm.
See also
Bibliography
- Intel, SEMICON West 2012.
- Intel, 2012 Symposia on VLSI Technology and Circuits (VLSI 2012).