Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon/cn3120-550bg868-scp"
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{{cavium title|CN3120-550 SCP}} | {{cavium title|CN3120-550 SCP}} | ||
{{chip | {{chip | ||
| − | + | | name = Cavium CN3120-550 SCP | |
| − | |name= | + | | no image = |
| − | |no image= | + | | image = octeon cn31xx.png |
| − | |image= | + | | image size = |
| − | + | | caption = | |
| − | + | | designer = Cavium | |
| − | |image size= | + | | manufacturer = TSMC |
| − | + | | model number = CN3120-550 SCP | |
| − | + | | part number = CN3120-550BG868-SCP | |
| − | |caption= | + | | part number 2 = |
| − | + | | part number 3 = | |
| − | + | | part number 4 = | |
| − | |designer | + | | market = Embedded |
| − | + | | first announced = January 30, 2006 | |
| − | + | | first launched = May 1, 2006 | |
| − | + | | last order = | |
| − | + | | last shipment = | |
| − | + | | release price = $125.00 | |
| − | + | ||
| − | |manufacturer | + | | family = OCTEON |
| − | |model number= | + | | series = CN3100 |
| − | |part number= | + | | locked = |
| − | |part number 2= | + | | frequency = 550 MHz |
| − | |part number 3= | + | | bus type = |
| − | + | | bus speed = | |
| − | + | | bus rate = | |
| − | + | | bus links = | |
| − | + | | clock multiplier = | |
| − | + | ||
| − | + | | isa family = MIPS | |
| − | |part number | + | | isa = MIPS64 |
| − | + | | microarch = cnMIPS | |
| − | + | | platform = | |
| − | + | | chipset = | |
| − | + | | core name = cnMIPS | |
| − | + | | core family = | |
| − | + | | core model = | |
| − | + | | core stepping = | |
| − | + | | process = 130 nm | |
| − | + | | transistors = | |
| − | + | | technology = CMOS | |
| − | + | | die area = <!-- XX mm² --> | |
| − | + | | die width = | |
| − | + | | die length = | |
| − | + | | word size = 64 bit | |
| − | + | | core count = 2 | |
| − | + | | thread count = 2 | |
| − | + | | max cpus = 1 | |
| − | + | | max memory = 4 GiB | |
| − | + | | max memory addr = | |
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| − | + | | power = 7 W | |
| − | + | | v core = | |
| − | + | | v core tolerance = | |
| − | + | | v io = | |
| − | |market | + | | v io tolerance = |
| − | + | | v io 2 = | |
| − | |first announced= | + | | v io 3 = |
| − | |first launched= | + | | sdp = |
| − | |last order= | + | | tdp = |
| − | |last shipment= | + | | tdp typical = |
| − | |release price= | + | | ctdp down = |
| − | + | | ctdp down frequency = | |
| − | + | | ctdp up = | |
| − | + | | ctdp up frequency = | |
| − | |family | + | | temp min = |
| − | |series= | + | | temp max = |
| − | + | | tjunc min = <!-- .. °C --> | |
| − | + | | tjunc max = | |
| − | + | | tcase min = | |
| − | + | | tcase max = | |
| − | + | | tstorage min = | |
| − | + | | tstorage max = | |
| − | + | | tambient min = | |
| − | + | | tambient max = | |
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| − | + | |package module 1={{packages/cavium/hsbga-868}} | |
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| − | |die area= | ||
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| − | |word size= | ||
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| − | |v core= | ||
| − | |v core tolerance= | ||
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| − | |v io= | ||
| − | |v io tolerance= | ||
| − | |v io 2= | ||
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| − | |sdp= | ||
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| − | |tdp | ||
| − | |tdp typical= | ||
| − | |ctdp down= | ||
| − | |ctdp down frequency= | ||
| − | |ctdp up= | ||
| − | |ctdp up frequency= | ||
| − | |temp min= | ||
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| − | |tjunc min= | ||
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| − | |tcase min= | ||
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}} | }} | ||
| − | The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, | + | The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. |
== Cache == | == Cache == | ||
Latest revision as of 21:22, 12 December 2024
| Edit Values | |||||||
| Cavium CN3120-550 SCP | |||||||
 | |||||||
| General Info | |||||||
| Designer | Cavium | ||||||
| Manufacturer | TSMC | ||||||
| Model Number | CN3120-550 SCP | ||||||
| Part Number | CN3120-550BG868-SCP | ||||||
| Market | Embedded | ||||||
| Introduction | January 30, 2006 (announced) May 1, 2006 (launched) | ||||||
| Release Price | $125.00 | ||||||
| General Specs | |||||||
| Family | OCTEON | ||||||
| Series | CN3100 | ||||||
| Frequency | 550 MHz | ||||||
| Microarchitecture | |||||||
| ISA | MIPS64 (MIPS) | ||||||
| Microarchitecture | cnMIPS | ||||||
| Core Name | cnMIPS | ||||||
| Process | 130 nm | ||||||
| Technology | CMOS | ||||||
| Word Size | 64 bit | ||||||
| Cores | 2 | ||||||
| Threads | 2 | ||||||
| Max Memory | 4 GiB | ||||||
| Multiprocessing | |||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||
| Electrical | |||||||
| Power dissipation | 7 W | ||||||
| Packaging | |||||||
| |||||||
The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Optional low-latency controller for content-based processing and meta data
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3120-550 SCP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3120-550 SCP - Cavium#package + |
| base frequency | 550 MHz (0.55 GHz, 550,000 kHz) + |
| core count | 2 + |
| core name | cnMIPS + |
| designer | Cavium + |
| family | OCTEON + |
| first announced | January 30, 2006 + |
| first launched | May 1, 2006 + |
| full page name | cavium/octeon/cn3120-550bg868-scp + |
| has ecc memory support | true + |
| has hardware accelerators for cryptography | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
| ldate | May 1, 2006 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
| max memory channels | 1 + |
| microarchitecture | cnMIPS + |
| model number | CN3120-550 SCP + |
| name | Cavium CN3120-550 SCP + |
| package | HSBGA-868 + |
| part number | CN3120-550BG868-SCP + |
| power dissipation | 7 W (7,000 mW, 0.00939 hp, 0.007 kW) + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| release price | $ 125.00 (€ 112.50, £ 101.25, ¥ 12,916.25) + |
| series | CN3100 + |
| smp max ways | 1 + |
| supported memory type | DDR2-667 + |
| technology | CMOS + |
| thread count | 2 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
