Semiconductor & Computer Engineering
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Difference between revisions of "Talk:ibm/microarchitectures/z15"
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:The Red Book is wrong. The SC chip has 12.2 billion xtors. Anyway 9.7 wouldn't even make sense (I think they originally mistakenly said 9.2B) because the z14 is 9.2B and they added 288 MiB of eDRAM which just the bitcells alone is 2.5B xtors + 2.5 caps, not including the rest of the logic. --[[User:David|David]] ([[User talk:David|talk]]) 11:41, 9 May 2020 (EDT) | :The Red Book is wrong. The SC chip has 12.2 billion xtors. Anyway 9.7 wouldn't even make sense (I think they originally mistakenly said 9.2B) because the z14 is 9.2B and they added 288 MiB of eDRAM which just the bitcells alone is 2.5B xtors + 2.5 caps, not including the rest of the logic. --[[User:David|David]] ([[User talk:David|talk]]) 11:41, 9 May 2020 (EDT) | ||
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| + | I believe the L4 on the z15 SC is 60 way set associative not 40 way | ||
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| + | Kurnal：I made a Die shot of IBM Telum, but I couldn't find the registration page or write data about Telum | ||
Latest revision as of 12:09, 29 November 2022
| This is the discussion page for the ibm/microarchitectures/z15 page. |
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Transistors[edit]
According to IBM redpapers, the SC chip has 9.7 billion transistors but the wiki entry shows 12.2 billion? — Preceding unsigned comment added by 99.82.166.5 (talk • contribs)
- The Red Book is wrong. The SC chip has 12.2 billion xtors. Anyway 9.7 wouldn't even make sense (I think they originally mistakenly said 9.2B) because the z14 is 9.2B and they added 288 MiB of eDRAM which just the bitcells alone is 2.5B xtors + 2.5 caps, not including the rest of the logic. --David (talk) 11:41, 9 May 2020 (EDT)
I believe the L4 on the z15 SC is 60 way set associative not 40 way
Kurnal：I made a Die shot of IBM Telum, but I couldn't find the registration page or write data about Telum