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+ | {{intel title|Cooper Lake|arch}} | ||
+ | {{microarchitecture | ||
+ | |atype=CPU | ||
+ | |name=Cooper Lake | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |introduction=June 18, 2020 | ||
+ | |process=14 nm++ | ||
+ | |cores=28 | ||
+ | |cores 2=24 | ||
+ | |cores 3=20 | ||
+ | |cores 4=18 | ||
+ | |cores 5=16 | ||
+ | |cores 6=8 | ||
+ | |type=Superscalar | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
+ | |stages min=14 | ||
+ | |stages max=19 | ||
+ | |isa=x86-64 | ||
+ | |extension=MOVBE | ||
+ | |extension 2=MMX | ||
+ | |extension 3=SSE | ||
+ | |extension 4=SSE2 | ||
+ | |extension 5=SSE3 | ||
+ | |extension 6=SSSE3 | ||
+ | |extension 7=SSE4.1 | ||
+ | |extension 8=SSE4.2 | ||
+ | |extension 9=POPCNT | ||
+ | |extension 10=AVX | ||
+ | |extension 11=AVX2 | ||
+ | |extension 12=AES | ||
+ | |extension 13=PCLMUL | ||
+ | |extension 14=FSGSBASE | ||
+ | |extension 15=RDRND | ||
+ | |extension 16=FMA3 | ||
+ | |extension 17=F16C | ||
+ | |extension 18=BMI | ||
+ | |extension 19=BMI2 | ||
+ | |extension 20=VT-x | ||
+ | |extension 21=VT-d | ||
+ | |extension 22=TXT | ||
+ | |extension 23=TSX | ||
+ | |extension 24=RDSEED | ||
+ | |extension 25=ADCX | ||
+ | |extension 26=PREFETCHW | ||
+ | |extension 27=CLFLUSHOPT | ||
+ | |extension 28=XSAVE | ||
+ | |extension 29=SGX | ||
+ | |extension 30=MPX | ||
+ | |extension 31=AVX-512 | ||
+ | |l1i=32 KiB | ||
+ | |l1i per=core | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d=32 KiB | ||
+ | |l1d per=core | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1=64 KiB | ||
+ | |l1 per=core | ||
+ | |l2=1 MiB | ||
+ | |l2 per=Core | ||
+ | |l2 desc=16-way set associative | ||
+ | |l3=1.375 MiB | ||
+ | |l3 per=core | ||
+ | |l3 desc=11-way set associative | ||
+ | |core name=Cooper Lake X | ||
+ | |core name 2=Cooper Lake SP | ||
+ | |core name 3=Cooper Lake AP | ||
+ | |predecessor=Cascade Lake | ||
+ | |predecessor link=intel/microarchitectures/cascade lake | ||
+ | |successor=Sapphire Rapids | ||
+ | |successor link=intel/microarchitectures/sapphire rapids | ||
+ | |contemporary=Ice Lake (Server) | ||
+ | |contemporary link=intel/microarchitectures/ice lake (server) | ||
+ | |contemporary 2=Coffee Lake | ||
+ | |contemporary 2 link=intel/microarchitectures/coffee lake | ||
+ | }} | ||
+ | '''Cooper Lake''' ('''CPL''' / '''CPX''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for the multiprocessing server market only. | ||
+ | Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while {{\\|Ice Lake (Server)|Ice Lake}} serves the single and dual-socket segments. | ||
+ | |||
+ | For scalable server class processors, Intel branded it as {{intel|Xeon Gold}} and {{intel|Xeon Platinum}}. | ||
+ | |||
+ | == Codenames == | ||
+ | Single and dual-socket Cooper Lake parts were scrapped before ever making it to market. | ||
+ | {| class="wikitable" | ||
+ | |- | ||
+ | ! Core !! Abbrev !! Target | ||
+ | |- style="text-decoration:line-through" | ||
+ | | {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market | ||
+ | |- style="text-decoration:line-through" | ||
+ | | {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations | ||
+ | |- | ||
+ | | {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors | ||
+ | |- style="text-decoration:line-through" | ||
+ | | {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors | ||
+ | |} | ||
+ | |||
+ | == Brands == | ||
+ | {{empty section}} | ||
+ | |||
+ | == Release Dates == | ||
+ | [[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]] | ||
+ | Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020. | ||
+ | |||
+ | == Process Technology == | ||
+ | Cooper Lake is fabricated on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]]. | ||
+ | |||
+ | == Architecture == | ||
+ | === Key changes from {{\\|Cascade Lake}} === | ||
+ | * SoC | ||
+ | ** 2x UPI links (6, up from 3) | ||
+ | |||
+ | * Memory | ||
+ | ** Higher data rate (3200 MT/s, up from 2933 MT/s) | ||
+ | ** Optane DC DIMMs | ||
+ | *** Apache Pass '''→''' Barlow Pass | ||
+ | |||
+ | * Platform | ||
+ | ** {{intel|Purley|l=platform}} '''→''' {{intel|Cedar Island|l=platform}} | ||
+ | |||
+ | * Packaging | ||
+ | ** Socket-P+ | ||
+ | *** 4189-contact flip-chip LGA (up from 3647 contacts) | ||
+ | {{expand list}} | ||
+ | |||
+ | ====New instructions ==== | ||
+ | Cooper Lake introduced a number of {{x86|extensions|new instructions}}: | ||
+ | |||
+ | * [[BFLOAT16]] - A new data type for [[acceleration]] of [[neural processor|AI workloads]]. | ||
+ | * {{x86|AVX512 BF16}} - AVX-512 [[Brain Float 16]] extension | ||
+ | |||
+ | == See also == | ||
+ | * {{\\|Ice Lake (Server)}} |
Latest revision as of 18:40, 26 March 2024
Edit Values | |
Cooper Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | June 18, 2020 |
Process | 14 nm++ |
Core Configs | 28, 24, 20, 18, 16, 8 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512 |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L1 Cache | 64 KiB/core |
L2 Cache | 1 MiB/Core 16-way set associative |
L3 Cache | 1.375 MiB/core 11-way set associative |
Cores | |
Core Names | Cooper Lake X, Cooper Lake SP, Cooper Lake AP |
Succession | |
Contemporary | |
Ice Lake (Server) Coffee Lake |
Cooper Lake (CPL / CPX) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for the multiprocessing server market only.
Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.
For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.
Contents
Codenames[edit]
Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.
Core | Abbrev | Target |
---|---|---|
Cooper Lake X | CPL-X | High-end desktops & enthusiasts market |
Cooper Lake W | CPL-W | Enterprise/Business workstations |
Cooper Lake SP | CPL-SP | Server Scalable Processors |
Cooper Lake AP | CPL-AP | Server Advanced Processors |
Brands[edit]
![]() |
This section is empty; you can help add the missing info by editing this page. |
Release Dates[edit]
![](/w/images/thumb/9/93/intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png/300px-intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png)
Cooper Lake and Ice Lake roadmap.
Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.
Process Technology[edit]
Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.
Architecture[edit]
Key changes from Cascade Lake[edit]
- SoC
- 2x UPI links (6, up from 3)
- Memory
- Higher data rate (3200 MT/s, up from 2933 MT/s)
- Optane DC DIMMs
- Apache Pass → Barlow Pass
- Platform
- Packaging
- Socket-P+
- 4189-contact flip-chip LGA (up from 3647 contacts)
- Socket-P+
This list is incomplete; you can help by expanding it.
New instructions[edit]
Cooper Lake introduced a number of new instructions:
- BFLOAT16 - A new data type for acceleration of AI workloads.
- AVX512 BF16 - AVX-512 Brain Float 16 extension
See also[edit]
Facts about "Cooper Lake - Microarchitectures - Intel"
codename | Cooper Lake + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/cooper lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cooper Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |