-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "Talk:intel/microarchitectures/spring hill"
m (Reverted edits by 185.136.159.30 (talk) to last revision by David) |
m (Undo revision 95645 by 188.163.109.153 (talk)) |
(11 intermediate revisions by 5 users not shown) | |
(No difference)
|
Latest revision as of 09:03, 29 January 2020
This is the discussion page for the intel/microarchitectures/spring hill page. |
|
2 chips[edit]
Any idea how the circuits are partitioned across the two chips shown in the package on the M.2 module? 82.102.30.46 14:05, 21 October 2019 (EDT)
- Spring Hill is a single die SoC. The second die on the package is actually the chipset and Intel confirmed it's the same PCH as Ice Lake. I added that information to the article. --David (talk) 04:50, 22 October 2019 (EDT)