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== 2 chips ==
 
Any idea how the circuits are partitioned across the two chips shown in the package on the M.2 module? [[Special:Contributions/82.102.30.46|82.102.30.46]] 14:05, 21 October 2019 (EDT)
 
Any idea how the circuits are partitioned across the two chips shown in the package on the M.2 module? [[Special:Contributions/82.102.30.46|82.102.30.46]] 14:05, 21 October 2019 (EDT)
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:Spring Hill is a single die SoC. The second die on the package is actually the chipset and Intel confirmed it's the same {{intel|ice lake (client)#PCH|PCH as Ice Lake|l=arch}}. I added that information to the article. --[[User:David|David]] ([[User talk:David|talk]]) 04:50, 22 October 2019 (EDT)

Latest revision as of 09:03, 29 January 2020

This is the discussion page for the intel/microarchitectures/spring hill page.

2 chips[edit]

Any idea how the circuits are partitioned across the two chips shown in the package on the M.2 module? 82.102.30.46 14:05, 21 October 2019 (EDT)

Spring Hill is a single die SoC. The second die on the package is actually the chipset and Intel confirmed it's the same PCH as Ice Lake. I added that information to the article. --David (talk) 04:50, 22 October 2019 (EDT)
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