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Difference between revisions of "intel/process-architecture-optimization"
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{{intel title|Process-Architecture-Optimization (PAO)}} | {{intel title|Process-Architecture-Optimization (PAO)}} | ||
| − | '''[[name::Process-Architecture-Optimization]]''' | + | '''[[name::Process-Architecture-Optimization]]''' was a temporary [[instance of::development model]] introduced by [[Intel]] for their mainstream microprocessors in [[2016]] following the phase-out of their {{intel|Tick-Tock}} model as a result of major delays and challenges involving their [[10 nm process]]. |
Under the Process-Architecture-Optimization Model: | Under the Process-Architecture-Optimization Model: | ||
| − | * '''Process''' - With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and | + | * '''Process''' - With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their {{intel|microarchitectures|previous}} [[microarchitecture]] to the new process which inherently yields better performance and energy saving. During a "process", usually, just a few features and improvements are introduced. |
* '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New [[instruction set|instructions]] are often added during this cycle stage. | * '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New [[instruction set|instructions]] are often added during this cycle stage. | ||
| − | * '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additionally the process itself enjoys various refinements as it matures. (For example with {{intel|Kaby Lake|l=arch}}, an optimized process called "14 nm+" is used. The enhanced process had a number of transistor-level modifications done to it (e.g. taller fins) allowing for higher frequency at identical voltage levels.) | + | * '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additionally, the process itself enjoys various refinements as it matures. (For example with {{intel|Kaby Lake|l=arch}}, an optimized process called "14 nm+" is used. The enhanced process had a number of transistor-level modifications done to it (e.g. taller fins) allowing for higher frequency at identical voltage levels.) |
== Roadmap == | == Roadmap == | ||
| Line 23: | Line 23: | ||
| Optimization || [[14 nm|14 nm+]] || 2016 || {{intel|Kaby Lake|l=arch}} | | Optimization || [[14 nm|14 nm+]] || 2016 || {{intel|Kaby Lake|l=arch}} | ||
|- | |- | ||
| − | | Optimization || [[14 nm|14 nm++]] || 2017 || {{intel|Coffee Lake|l=arch}} | + | | Optimization || [[14 nm|14 nm++]] || 2017 || {{intel|Coffee Lake|l=arch}}, {{intel|Skylake (Server)|l=arch}} |
|- | |- | ||
| − | | Optimization || [[14 nm|14 nm++]] || 2018 || {{intel|Whiskey Lake|l=arch}} | + | | Optimization || [[14 nm|14 nm++]] || 2018 || {{intel|Amber Lake|l=arch}} {{intel|Whiskey Lake|l=arch}} |
|- | |- | ||
| − | | Optimization || [[14 nm|14 nm++]] || | + | | Optimization || [[14 nm|14 nm++]] || 2019 || {{intel|Cascade Lake|l=arch}} |
|- | |- | ||
| − | | Optimization || [[14 nm|14 nm++]] || | + | | Optimization || [[14 nm|14 nm++]] || 2020 || {{intel|Cooper Lake|l=arch}}, {{intel|Comet Lake|l=arch}} |
| + | |- | ||
| + | | Optimization || [[14 nm|14 nm++]] || 2021 || {{intel|Rocket Lake|l=arch}} | ||
|} | |} | ||
[[Category:intel]] | [[Category:intel]] | ||
Latest revision as of 20:33, 8 November 2019
Process-Architecture-Optimization was a temporary development model introduced by Intel for their mainstream microprocessors in 2016 following the phase-out of their Tick-Tock model as a result of major delays and challenges involving their 10 nm process.
Under the Process-Architecture-Optimization Model:
- Process - With each process, Intel advances their manufacturing process technology in line with Moore's Law. Each new process introduces higher transistor density and generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their previous microarchitecture to the new process which inherently yields better performance and energy saving. During a "process", usually, just a few features and improvements are introduced.
- Architecture - With each architecture, Intel uses the their latest manufacturing process technology from their "process" to manufacture a newly designed microarchitecture. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New instructions are often added during this cycle stage.
- Optimization - With each optimization, Intel improves upon their previous microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additionally, the process itself enjoys various refinements as it matures. (For example with Kaby Lake, an optimized process called "14 nm+" is used. The enhanced process had a number of transistor-level modifications done to it (e.g. taller fins) allowing for higher frequency at identical voltage levels.)
Roadmap[edit]
| Intel PAO Roadmap | |||
|---|---|---|---|
| Cycle | Process | Introduction | Microarchitecture |
| Process | 14 nm | 2014 | Broadwell |
| Architecture | 14 nm | 2015 | Skylake (Client) |
| Optimization | 14 nm+ | 2016 | Kaby Lake |
| Optimization | 14 nm++ | 2017 | Coffee Lake, Skylake (Server) |
| Optimization | 14 nm++ | 2018 | Amber Lake Whiskey Lake |
| Optimization | 14 nm++ | 2019 | Cascade Lake |
| Optimization | 14 nm++ | 2020 | Cooper Lake, Comet Lake |
| Optimization | 14 nm++ | 2021 | Rocket Lake |
Facts about "Process-Architecture-Optimization (PAO) - Intel"
| instance of | development model + |
| name | Process-Architecture-Optimization + |