From WikiChip
Difference between revisions of "intel/xeon e5/e5-2670 v3"
(Create page for Xeon E5-2670 v3) |
(→Memory controller: fixed a typo) |
||
(6 intermediate revisions by 3 users not shown) | |||
Line 2: | Line 2: | ||
{{chip | {{chip | ||
|name=Xeon E5-2670 v3 | |name=Xeon E5-2670 v3 | ||
+ | |image=E5-2670v3.jpg | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
Line 8: | Line 9: | ||
|part number 2=BX80644E52670V3 | |part number 2=BX80644E52670V3 | ||
|s-spec=SR1XS | |s-spec=SR1XS | ||
− | |s-spec qs=QGP2 | + | |s-spec qs=QFS0 |
+ | |s-spec qs 2=QGP2 | ||
|market=Server | |market=Server | ||
|first announced=September 8, 2014 | |first announced=September 8, 2014 | ||
Line 29: | Line 31: | ||
|turbo frequency11=2,600 MHz | |turbo frequency11=2,600 MHz | ||
|turbo frequency12=2,600 MHz | |turbo frequency12=2,600 MHz | ||
+ | |turbo frequency=Yes | ||
|bus type=QPI | |bus type=QPI | ||
|bus speed=4,800 MHz | |bus speed=4,800 MHz | ||
Line 51: | Line 54: | ||
|thread count=24 | |thread count=24 | ||
|max cpus=2 | |max cpus=2 | ||
− | |max memory=786 | + | |max memory=786 GiB |
|v core=1.82 V | |v core=1.82 V | ||
|v io=1.2 V | |v io=1.2 V | ||
Line 60: | Line 63: | ||
|tstorage min=-25 °C | |tstorage min=-25 °C | ||
|tstorage max=125 °C | |tstorage max=125 °C | ||
− | |||
|die size=306.18 mm² | |die size=306.18 mm² | ||
|packaging=Yes | |packaging=Yes | ||
Line 73: | Line 75: | ||
|socket 0 type=LGA | |socket 0 type=LGA | ||
}} | }} | ||
− | The '''Xeon E5-2670 v3''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2014. This server MPU is designed for 2S | + | The '''Xeon E5-2670 v3''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2014. This server MPU is designed for 2S environments. Operating at 2.3 GHz with a {{intel|turbo boost}} frequency of 3.1 GHz for two active cores, this MPU has a TDP of 120 W and is manufactured on a [[22 nm process]] (based on {{intel|Haswell|l=arch}}). |
== Cache == | == Cache == | ||
Line 105: | Line 107: | ||
| channels = 4 | | channels = 4 | ||
| ecc support = Yes | | ecc support = Yes | ||
− | | max bandwidth = 69. | + | | max bandwidth = 69.63 GiB/s |
− | | bandwidth schan = 17. | + | | bandwidth schan = 17.40 GiB/s |
− | | bandwidth dchan = 34. | + | | bandwidth dchan = 34.81 GiB/s |
− | | max memory = | + | | max memory = 768 GiB |
| pae = 46 bit | | pae = 46 bit | ||
}} | }} | ||
Line 123: | Line 125: | ||
== Features == | == Features == | ||
{{x86 features | {{x86 features | ||
− | | | + | |real=No |
− | | nx | + | |protected=No |
− | | | + | |smm=No |
− | | | + | |fpu=Yes |
− | | | + | |x8616=No |
− | | | + | |x8632=Yes |
− | | | + | |x8664=Yes |
− | | | + | |nx=Yes |
− | | | + | |mmx=Yes |
− | | | + | |emmx=No |
− | | | + | |sse=Yes |
− | | | + | |sse2=Yes |
− | | | + | |sse3=Yes |
− | | | + | |ssse3=Yes |
− | | | + | |sse41=Yes |
− | | | + | |sse42=Yes |
− | | | + | |sse4a=No |
− | | | + | |avx=Yes |
− | | | + | |avx2=Yes |
− | | | + | |avx512f=No |
− | | | + | |avx512cd=No |
− | | | + | |avx512er=No |
− | | | + | |avx512pf=No |
− | | | + | |avx512bw=No |
− | | | + | |avx512dq=No |
− | | | + | |avx512vl=No |
− | | | + | |avx512ifma=No |
− | | | + | |avx512vbmi=No |
− | | | + | |avx5124fmaps=No |
− | | mpx | + | |avx512vnni=No |
− | | sgx | + | |avx5124vnniw=No |
− | | | + | |avx512vpopcntdq=No |
− | | | + | |abm=Yes |
− | | | + | |tbm=No |
− | | | + | |bmi1=Yes |
− | | | + | |bmi2=Yes |
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=Yes | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | |em64t=Yes | ||
+ | |vt-x=Yes | ||
+ | |vt-d=Yes | ||
+ | |sse4_1=Yes | ||
+ | |sse4_2=Yes | ||
+ | |pclmul=Yes | ||
+ | |bmi=Yes | ||
+ | |secure key=Yes | ||
+ | |os guard=Yes | ||
}} | }} |
Latest revision as of 04:17, 9 April 2022
Edit Values | |
Xeon E5-2670 v3 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | E5-2670 v3 |
Part Number | CM8064401544801, BX80644E52670V3 |
S-Spec | SR1XS QFS0 (QS), QGP2 (QS) |
Market | Server |
Introduction | September 8, 2014 (announced) September 8, 2014 (launched) |
Release Price | $1589.00 |
Shop | Amazon |
General Specs | |
Family | Xeon E5 |
Series | E5-2600 |
Locked | Yes |
Frequency | 2,300 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 3,100 MHz (1 core), 3,100 MHz (2 cores), 2,900 MHz (3 cores), 2,800 MHz (4 cores), 2,700 MHz (5 cores), 2,600 MHz (6 cores), 2,600 MHz (7 cores), 2,600 MHz (8 cores), 2,600 MHz (9 cores), 2,600 MHz (10 cores), 2,600 MHz (11 cores), 2,600 MHz (12 cores) |
Bus type | QPI |
Bus speed | 4,800 MHz |
Bus rate | 2 × 9.6 GT/s |
Clock multiplier | 23 |
CPUID | 306F2 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Haswell |
Platform | Grantley EP 2S |
Chipset | C610 Series |
Core Name | Haswell EP |
Core Family | 6 |
Core Model | 3F |
Core Stepping | M1 |
Process | 22 nm |
Transistors | 4,700,000,000 |
Technology | CMOS |
Die | 306.18 mm² |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 786 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
Vcore | 1.82 V |
VI/O | 1.2 V ± 3% |
TDP | 120 W |
Tcase | 0 °C – 76 °C |
Tstorage | -25 °C – 125 °C |
The Xeon E5-2670 v3 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2014. This server MPU is designed for 2S environments. Operating at 2.3 GHz with a turbo boost frequency of 3.1 GHz for two active cores, this MPU has a TDP of 120 W and is manufactured on a 22 nm process (based on Haswell).
Cache[edit]
- Main article: Haswell § Cache
Cache Info [Edit Values] | ||
L1I$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
L2$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
12x256 KiB 8-way set associative (per core, write-back) |
L3$ | 30 MiB 30,720 KiB 31,457,280 B 0.0293 GiB |
12x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR4-2133 |
Controllers | 2 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 69.63 GiB/s |
Bandwidth (single) | 17.40 GiB/s |
Bandwidth (dual) | 34.81 GiB/s |
Max memory | 768 GiB |
Physical Address Extensions | 46 bit |
Expansions[edit]
Expansion Options
|
||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||
|
Facts about "Xeon E5-2670 v3 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-2670 v3 - Intel#io + |
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
bus links | 2 + |
bus rate | 9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) + |
bus speed | 4,800 MHz (4.8 GHz, 4,800,000 kHz) + |
bus type | QPI + |
chipset | C610 Series + |
clock multiplier | 23 + |
core count | 12 + |
core family | 6 + |
core model | 3F + |
core name | Haswell EP + |
core stepping | M1 + |
core voltage | 1.82 V (18.2 dV, 182 cV, 1,820 mV) + |
cpuid | 306F2 + |
designer | Intel + |
die area | 306.18 mm² (0.475 in², 3.062 cm², 306,180,000 µm²) + |
family | Xeon E5 + |
first announced | September 8, 2014 + |
first launched | September 8, 2014 + |
full page name | intel/xeon e5/e5-2670 v3 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Secure Key Technology + and OS Guard + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
io voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
io voltage tolerance | 3% + |
isa | x86-64 + |
isa family | x86 + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) + |
ldate | September 8, 2014 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 349.15 K (76 °C, 168.8 °F, 628.47 °R) + |
max cpu count | 2 + |
max memory | 804,864 MiB (824,180,736 KiB, 843,961,073,664 B, 786 GiB, 0.768 TiB) + |
max pcie lanes | 40 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Haswell + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | E5-2670 v3 + |
name | Xeon E5-2670 v3 + |
part number | CM8064401544801 + and BX80644E52670V3 + |
platform | Grantley EP 2S + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + |
release price | $ 1,589.00 (€ 1,430.10, £ 1,287.09, ¥ 164,191.37) + |
s-spec | SR1XS + |
s-spec (qs) | QFS0 + and QGP2 + |
series | E5-2600 + |
smp max ways | 2 + |
tdp | 120 W (120,000 mW, 0.161 hp, 0.12 kW) + |
technology | CMOS + |
thread count | 24 + |
transistor count | 4,700,000,000 + |
turbo frequency (10 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (11 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (12 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (1 core) | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
turbo frequency (2 cores) | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
turbo frequency (3 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (4 cores) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
turbo frequency (5 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (6 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (7 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (8 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (9 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |