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Difference between revisions of "arm/armv8.1"
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ARMv8.1 is an extension to {{\\|ARMv8}}, an [[ARM]] [[instruction set architecture]] which brought a large number of fundamental changes to the instruction set, including the introduction of 64-bit operating capabilities. | ARMv8.1 is an extension to {{\\|ARMv8}}, an [[ARM]] [[instruction set architecture]] which brought a large number of fundamental changes to the instruction set, including the introduction of 64-bit operating capabilities. | ||
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* Large System Extensions (LSE) | * Large System Extensions (LSE) | ||
** New atomic instructions to support scalable performance: | ** New atomic instructions to support scalable performance: | ||
| − | ** Most of the following have optional load-acquire and/or store-release semantics | + | ** Instructions for full-word, half-word, and byte operations are available. |
| + | ** Most of the following have optional load-acquire and/or store-release semantics. | ||
*** Compare and Swap: CAS, CASP (up to 128-bit values). | *** Compare and Swap: CAS, CASP (up to 128-bit values). | ||
*** Atomic Memory Operations: ADD, CLR, EOR, SET, MAX (signed/unsigned), MIN (signed/unsigned). | *** Atomic Memory Operations: ADD, CLR, EOR, SET, MAX (signed/unsigned), MIN (signed/unsigned). | ||
**** LD<op> versions return the value of the updated memory (LDADD for example). | **** LD<op> versions return the value of the updated memory (LDADD for example). | ||
**** ST<op> versions are "fire-and-forget" (STADD for example). | **** ST<op> versions are "fire-and-forget" (STADD for example). | ||
| − | *** | + | *** SWAP |
* Rounding Double Multiply Add/Subtract instruction (RDMA) | * Rounding Double Multiply Add/Subtract instruction (RDMA) | ||
* Limited Ordering Regions (LOR) | * Limited Ordering Regions (LOR) | ||
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== Optional Features in ARMv8.1 == | == Optional Features in ARMv8.1 == | ||
* Hierarchical permission disables (HPD) | * Hierarchical permission disables (HPD) | ||
| − | * 16- | + | * 16-bit VMID (VMID16) |
* PMU Extensions (PMU) | * PMU Extensions (PMU) | ||
Latest revision as of 09:38, 16 January 2020
| ARM ISA | |
| General | |
| Variants | |
| Extensions | |
| Topics | |
| Versions(all) | |
ARMv8.1 is an extension to ARMv8, an ARM instruction set architecture which brought a large number of fundamental changes to the instruction set, including the introduction of 64-bit operating capabilities.
Mandatory Features from ARMv8.0[edit]
- CRC32 was optional in ARMv8.0, now mandatory.
Mandatory Features in ARMv8.1[edit]
- Large System Extensions (LSE)
- New atomic instructions to support scalable performance:
- Instructions for full-word, half-word, and byte operations are available.
- Most of the following have optional load-acquire and/or store-release semantics.
- Compare and Swap: CAS, CASP (up to 128-bit values).
- Atomic Memory Operations: ADD, CLR, EOR, SET, MAX (signed/unsigned), MIN (signed/unsigned).
- LD<op> versions return the value of the updated memory (LDADD for example).
- ST<op> versions are "fire-and-forget" (STADD for example).
- SWAP
- Rounding Double Multiply Add/Subtract instruction (RDMA)
- Limited Ordering Regions (LOR)
- Privileged access never (PAN)
- Virtualization Host Extensions (VHE)
Optional Features in ARMv8.1[edit]
- Hierarchical permission disables (HPD)
- 16-bit VMID (VMID16)
- PMU Extensions (PMU)