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'''ARM11''' is the successor to the {{armh|ARM10|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The ARM11 was designed by the Arm Sophia-Antipolis design center.
 
'''ARM11''' is the successor to the {{armh|ARM10|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The ARM11 was designed by the Arm Sophia-Antipolis design center.
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== Architecture ==
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=== Key changes from {{\\|ARM10}}===
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{{empty section}}
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=== Block Diagram ===
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{{empty section}}
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=== Memory Hierarchy ===
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{{empty section}}
 +
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== Licensees ==
 +
In 2013 Arm reported 82 licensees. The following were named.
 +
 +
{{collist
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|count = 3
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|
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'''ARM11 MPCore'''
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* [[Intel]]
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* [[Corporation]]
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* [[NEC]]
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* [[Electronics]]
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* [[Netronome]]
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* [[NVIDIA]]
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* [[PMC]]
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* [[Sierra]]
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* [[Renesas]]
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* [[Sarnoff]]
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'''ARM1176JZ(F)-S'''
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* [[Broadcom]]
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* [[Corporation]]
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* [[Infineon]]
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* [[Technologies]]
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* [[AG]]
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* [[Matsushita]]
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* [[NEC]]
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* [[Electronics]]
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* [[NXP,Renesas]]
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* [[Sunplus]]
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* [[Texas]]
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* [[Instruments]]
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* [[Toshiba]]
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'''ARM1156T2(F)-S'''
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* [[Comsys]]
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* [[LSI]]
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* [[Logic]]
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* [[NEC]]
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* [[Electronics]]
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'''ARM1136J(F)-S''':
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* [[Accent]]
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* [[Broadcom]]
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* [[Corporation]]
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* [[Ceroma]]
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* [[eSilicon]]
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* [[Corporation]]
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* [[Freescale]]
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* [[Semiconductor]]
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* [[LSI]]
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* [[Logic]]
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* [[Matsushita]]
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* [[Mindspeed]]
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* [[NEC]]
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* [[Electronics]]
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* [[Qualcomm]]
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* [[Renesas]]
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* [[STMicroelectronics]]
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* [[Texas]]
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* [[Instruments]]
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* [[Toshiba]]
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}}
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== Die ==
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* [[0.35 μm process]]
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* 5.55 mm² die size (with cache)
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* 2.85 mm² die size (without cache)
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* 333-550 MHz max frequency
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* 0.8 mW/MHz with cache
 +
* 0.6 mW/MHz without cache

Latest revision as of 04:05, 31 December 2018

Edit Values
ARM11 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionApril 29, 2002
Succession

ARM11 is the successor to the ARM10, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as an IP core and is sold to other semiconductor companies to be implemented in their own chips. The ARM11 was designed by the Arm Sophia-Antipolis design center.

Architecture[edit]

Key changes from ARM10[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Licensees[edit]

In 2013 Arm reported 82 licensees. The following were named.

ARM11 MPCore

ARM1176JZ(F)-S

ARM1156T2(F)-S

ARM1136J(F)-S:

Die[edit]

  • 0.35 μm process
  • 5.55 mm² die size (with cache)
  • 2.85 mm² die size (without cache)
  • 333-550 MHz max frequency
  • 0.8 mW/MHz with cache
  • 0.6 mW/MHz without cache
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/arm11&oldid=85485"
Facts about "ARM11 - Microarchitectures - ARM"
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codenameARM11 +
designerARM Holdings +
first launchedApril 29, 2002 +
full page namearm holdings/microarchitectures/arm11 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameARM11 +