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Difference between revisions of "arm holdings/microarchitectures/cortex-a73"
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| − | '''Cortex-A73''' (codename '''Artemis''') is the successor to the {{armh|Cortex-A72|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A73, which implemented the {{arm|ARMv8}} ISA, is the | + | '''Cortex-A73''' (codename '''Artemis''') is the successor to the {{armh|Cortex-A72|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A73, which implemented the {{arm|ARMv8}} ISA, is the performance core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance. |
| + | |||
| + | == Compiler support == | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Arch-Specific || Arch-Favorable | ||
| + | |- | ||
| + | | [[Arm Compiler]] || <code>-mcpu=cortex-a73</code> || <code>-mtune=cortex-a73</code> | ||
| + | |- | ||
| + | | [[GCC]] || <code>-mcpu=cortex-a73</code> || <code>-mtune=cortex-a73</code> | ||
| + | |- | ||
| + | | [[LLVM]] || <code>-mcpu=cortex-a73</code> || <code>-mtune=cortex-a73</code> | ||
| + | |} | ||
| + | |||
| + | If the Cortex-A73 is coupled with the {{\\|Cortex-A53}} in a [[big.LITTLE]] system, GCC also supports the following option: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Tune | ||
| + | |- | ||
| + | | [[GCC]] || <code>-mtune=cortex-a73.cortex-a53</code> | ||
| + | |} | ||
| + | |||
| + | == Architecture == | ||
| + | === Key changes from {{\\|Cortex-A72}} === | ||
| + | {{empty section}} | ||
| + | === Block Diagram === | ||
| + | {{empty section}} | ||
| + | === Memory Hierarchy === | ||
| + | {{empty section}} | ||
Latest revision as of 22:49, 4 April 2021
| Edit Values | |
| Cortex-A73 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | May 29, 2016 |
| Instructions | |
| ISA | ARMv8 |
| Succession | |
Cortex-A73 (codename Artemis) is the successor to the Cortex-A72, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A73, which implemented the ARMv8 ISA, is the performance core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.
Contents
Compiler support[edit]
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| Arm Compiler | -mcpu=cortex-a73 |
-mtune=cortex-a73
|
| GCC | -mcpu=cortex-a73 |
-mtune=cortex-a73
|
| LLVM | -mcpu=cortex-a73 |
-mtune=cortex-a73
|
If the Cortex-A73 is coupled with the Cortex-A53 in a big.LITTLE system, GCC also supports the following option:
| Compiler | Tune |
|---|---|
| GCC | -mtune=cortex-a73.cortex-a53
|
Architecture[edit]
Key changes from Cortex-A72[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Block Diagram[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Cortex-A73 - Microarchitectures - ARM"
| codename | Cortex-A73 + |
| designer | ARM Holdings + |
| first launched | May 29, 2016 + |
| full page name | arm holdings/microarchitectures/cortex-a73 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A73 + |