Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/thunderx"
(add referrences) |
|||
| (2 intermediate revisions by 2 users not shown) | |||
| Line 31: | Line 31: | ||
== Overview == | == Overview == | ||
The ThunderX was [[Cavium]]'s first server-class [[ARMv8]] processor based on custom {{cavium|ThunderX1|l=arch}} core, announced in 2014. | The ThunderX was [[Cavium]]'s first server-class [[ARMv8]] processor based on custom {{cavium|ThunderX1|l=arch}} core, announced in 2014. | ||
| − | Available in single and dual socket configurations | + | Available in single and dual socket configurations using Cavium Coherent Processor Interconnect (CCPI™). Up to 4 DDR3/4 memory controllers. |
| + | |||
| + | == Compiler Support == | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target | ||
| + | |- | ||
| + | | [[GCC]] || <code>-march=armv8-a</code> || <code>-mtune=thunderx</code> || <code>-mcpu=thunderx</code> | ||
| + | |- | ||
| + | | [[LLVM]] || <code>-march=armv8-a</code> || <code>-mtune=thunderx</code> || <code>-mcpu=thunderx</code> | ||
| + | |} | ||
== Models == | == Models == | ||
| Line 81: | Line 91: | ||
* Qualcomm's {{qualcomm|Centriq}} | * Qualcomm's {{qualcomm|Centriq}} | ||
* Intel's {{intel|Xeon Platinum}}, {{intel|Xeon Gold|Gold}}, and {{intel|Xeon Silver|Silver}} | * Intel's {{intel|Xeon Platinum}}, {{intel|Xeon Gold|Gold}}, and {{intel|Xeon Silver|Silver}} | ||
| + | * Cavium {{cavium|ThunderX2}}. | ||
Latest revision as of 13:02, 19 May 2021
| ThunderX | |
| Developer | Cavium |
| Type | Microprocessors |
| Introduction | June 3, 2014 (announced) Dec 1, 2014 (launch) |
| ISA | ARMv8 |
| µarch | ThunderX |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 28 nm 0.028 μm
2.8e-5 mm |
| Technology | CMOS |
| Clock | 2,000 MHz-2,500 MHz |
| Succession | |
| → | |
| ThunderX2 | |
ThunderX is a family of 64-bit multi-core ARM server microprocessors introduced by Cavium.
Overview[edit]
The ThunderX was Cavium's first server-class ARMv8 processor based on custom ThunderX1 core, announced in 2014. Available in single and dual socket configurations using Cavium Coherent Processor Interconnect (CCPI™). Up to 4 DDR3/4 memory controllers.
Compiler Support[edit]
| Compiler | Arch-Specific | Arch-Favorable | Arch-Target |
|---|---|---|---|
| GCC | -march=armv8-a |
-mtune=thunderx |
-mcpu=thunderx
|
| LLVM | -march=armv8-a |
-mtune=thunderx |
-mcpu=thunderx
|
Models[edit]
CN88xx[edit]
- See also: ThunderX1 microarchitecture
The first parts of the ThunderX family, CN88xx series are based on the ThunderX1 microarchitecture. All parts have the following features in common.
- Mem: Up to 1 TiB of quad/hexa/octa- channel DDR3/4 2400 MT/s memory
- Up to 1 TiB in dual-socket configuration
- ISA: ARMv8, 128-bit NEON SIMD
- I/O: "multiple" PCIe Gen 3 Lanes
- Only the 64-bit AArch64 execution state is support. No 32-bit AArch32 support.
| List of ThunderX1 Processors | |||||
|---|---|---|---|---|---|
| Main processor | |||||
| Model | Launched | Cores | Threads | Frequency | PCIe Lanes |
| CN8890 | 31 March 2016 | 48 | 48 | 1.9 GHz 1,900 MHz 1,900,000 kHz | |
| Count: 1 | |||||
See also[edit]
- ThunderX® ARM Processors Archive
- Investigating Cavium's ThunderX: The First ARM Server SoC With Ambition
- Exploring a production Cavium ThunderX platform with a Gigabyte R120-T30 1U server
- TIRIAS ThunderX Memecached TCO white paper
- Qualcomm's Centriq
- Intel's Xeon Platinum, Gold, and Silver
- Cavium ThunderX2.
Facts about "ThunderX - Cavium"
| designer | Cavium + |
| first announced | June 3, 2014 + |
| first launched | December 1, 2014 + |
| full page name | cavium/thunderx + |
| instance of | microprocessor family + |
| instruction set architecture | ARMv8 + |
| main designer | Cavium + |
| microarchitecture | ThunderX + |
| name | ThunderX + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |