Semiconductor & Computer Engineering
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== Overview == | == Overview == | ||
[[File:intel turbo velocity boost.png|right|400px]] | [[File:intel turbo velocity boost.png|right|400px]] | ||
| − | For devices with premium cooling solutions, microprocessors with {{intel|Turbo Boost}} support and TVB support enabled, the processor can automatically increase the clock frequency by up to an additional | + | For devices with premium cooling solutions, microprocessors with {{intel|Turbo Boost}} support and TVB support enabled, the processor can automatically increase the clock frequency by up to an additional few bins if T<sub>CASE</sub> is at a certain temperature or lower and turbo power budget is available. Though unlikely to be sustainable and will drop once the temperature threshold is exceeded, for highly bursty workloads (such as what impacts the user experience the most), the performance increase can be fairly significant. |
| + | |||
| + | === Up bins === | ||
| + | The exact number of bins and temperature depends on the processor (mobile, desktop \ 15W, 45W, 65W): | ||
| + | |||
| + | * For {{intel|Coffee Lake H|l=core}}, TVB is +200 MHz if T<sub>CASE</sub> is at 50°C or lower and turbo power budget is available. | ||
| + | * For {{intel|Coffee Lake R|l=core}}, {{intel|Whiskey Lake U|l=core}}, and {{intel|Comet Lake U |l=core}}, TVB is +100 MHz if T<sub>CASE</sub> is at 70°C or lower and turbo power budget is available. | ||
| + | * For {{intel|Comet Lake H|l=core}}, TVB is +200 MHz if T<sub>CASE</sub> is at 65°C or lower and turbo power budget is available. | ||
| + | |||
| + | |||
| + | For S processors, like the i9 9900k, Thermal Velocity Boost's clock up-bins are disabled by default, but VID optimizations are usually enabled on many mainboards. | ||
| + | Gigabyte and Asus are known to enable these voltage optimizations by default. | ||
| + | VID optimizations allow the CPU to reduce its requested VID by 1.5mv, every 1C temp drop, starting at 100C and going down to 0C. | ||
| + | Therefore, there is a 150mv VID spread, between 100C and 0C. So as the processor cools, the requested VID decreases. | ||
| + | This reduction is strongest at x50 core multiplier, and slowly decreases in magnitude down to x40, with no reduction below x40. | ||
| + | Disabling TvB voltage optimizations will make the base CPU VID equal to the TJMax point for that multiplier instead (as if TvB were enabled). | ||
== History == | == History == | ||
| − | TVB was introduced with {{intel|Coffee Lake H|l=core}} parts. | + | * TVB was introduced with {{intel|Coffee Lake H|l=core}} mobile parts. |
| + | * TVB was added to some desktop parts for the first in {{intel|Coffee Lake R|l=core}}. | ||
== See also == | == See also == | ||
Latest revision as of 16:23, 9 August 2021
Thermal Velocity Boost (TVB) is a microprocessor technology developed by Intel that attempts to enable temporary higher performance on top of Turbo Boost Technology by opportunistically and automatically increasing the processor's clock frequency.
Contents
Overview[edit]
For devices with premium cooling solutions, microprocessors with Turbo Boost support and TVB support enabled, the processor can automatically increase the clock frequency by up to an additional few bins if TCASE is at a certain temperature or lower and turbo power budget is available. Though unlikely to be sustainable and will drop once the temperature threshold is exceeded, for highly bursty workloads (such as what impacts the user experience the most), the performance increase can be fairly significant.
Up bins[edit]
The exact number of bins and temperature depends on the processor (mobile, desktop \ 15W, 45W, 65W):
- For Coffee Lake H, TVB is +200 MHz if TCASE is at 50°C or lower and turbo power budget is available.
- For Coffee Lake R, Whiskey Lake U, and Comet Lake U , TVB is +100 MHz if TCASE is at 70°C or lower and turbo power budget is available.
- For Comet Lake H, TVB is +200 MHz if TCASE is at 65°C or lower and turbo power budget is available.
For S processors, like the i9 9900k, Thermal Velocity Boost's clock up-bins are disabled by default, but VID optimizations are usually enabled on many mainboards.
Gigabyte and Asus are known to enable these voltage optimizations by default.
VID optimizations allow the CPU to reduce its requested VID by 1.5mv, every 1C temp drop, starting at 100C and going down to 0C.
Therefore, there is a 150mv VID spread, between 100C and 0C. So as the processor cools, the requested VID decreases.
This reduction is strongest at x50 core multiplier, and slowly decreases in magnitude down to x40, with no reduction below x40.
Disabling TvB voltage optimizations will make the base CPU VID equal to the TJMax point for that multiplier instead (as if TvB were enabled).
History[edit]
- TVB was introduced with Coffee Lake H mobile parts.
- TVB was added to some desktop parts for the first in Coffee Lake R.
See also[edit]
- Frequency behavior of Intel processors