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|-
 
|-
 
| STC || 1B || 1 || 1 || C ← 1 || Set carry flag ||  
 
| STC || 1B || 1 || 1 || C ← 1 || Set carry flag ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
 
| XC || 1A || 1 || 1 || C ↔ C' || Exchange carry flag with carry save ||
 
| XC || 1A || 1 || 1 || C ↔ C' || Exchange carry flag with carry save ||
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
 
| RAR || 30 || 1 || 1 || C → A<sub>CC</sub> → C || Rotate accumulator right through carry flag ||  
 
| RAR || 30 || 1 || 1 || C → A<sub>CC</sub> → C || Rotate accumulator right through carry flag ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| INM || 1D || 1 || 1 + skip || (DP) = (DP) + 1 || Increment RAM location pointed by DP, skip if result is zero || on (DP) = 0
+
| INM || 1D || 1 || 1 + skip || (DP) = (DP) + 1 || Increment RAM content pointed by DP, skip if result is zero || on (DP) = 0
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| DEM || 1F || 1 || 1 + skip || (DP) = (DP) - 1 || Decrement RAM location pointed by DP, skip if result is 0Fh || on (DP) = 0Fh
+
| DEM || 1F || 1 || 1 + skip || (DP) = (DP) - 1 || Decrement RAM content pointed by DP, skip if result is 0Fh || on (DP) = 0Fh
 
|-
 
|-
−
| AD || || 1 ||  
+
| AD || 08 || 1 || 1 + skip || A<sub>CC</sub> ← A<sub>CC</sub> + (DP) || Add RAM content pointed by DP to accumulator, skip if overflow || on overflow
 
|-
 
|-
−
| ADS || || 1 ||  
+
| ADS || 09 || 1 || 1 + skip || A<sub>CC</sub> ← A<sub>CC</sub> + (DP) + C<br />C ← 1 on overflow || Add RAM content pointed by DP with carry to accumulator<br />If overflow set carry flag and skip || on overflow 
 
|-
 
|-
−
| ADC || || 1 ||  
+
| ADC || 19 || 1 || 1 || A<sub>CC</sub> ← A<sub>CC</sub> + (DP) + C<br />C ← 1 on overflow || Add RAM content pointed by DP with carry to accumulator<br />If overflow set carry flag ||  
 
|-
 
|-
−
| DAA || || 1 ||  
+
| DAA || 06 || 1 || 1 || A<sub>CC</sub> ← A<sub>CC</sub> + 6 || Decimal adjust accumulator for BCD addition ||  
 
|-
 
|-
−
| DAS || || 1 ||  
+
| DAS || 0A || 1 || 1 || A<sub>CC</sub> ← A<sub>CC</sub> + 10 || Decimal adjust accumulator for BCD subtraction ||  
 
|-
 
|-
−
| EXL || || 1 ||  
+
| EXL || 18 || 1 || 1 || A<sub>CC</sub> ← A<sub>CC</sub> ^ (DP) || Exclusive-or accumulator with RAM content pointed by DP ||  
 
|-
 
|-
−
| LI || || 1 ||  
+
| LI || 90 + D[3:0] || 1 || 1 || A<sub>CC</sub> ← D[3:0] || Load accumulator with immediate data D[3:0] || 
 
|-
 
|-
−
| S || || 1 ||  
+
| S || 02 || 1 || 1 || (DP) ← A<sub>CC</sub> || Store accumulator into RAM location pointed by DP || 
 
|-
 
|-
−
| L || || 1 ||  
+
| L || 38 || 1 || 1 || A<sub>CC</sub> ← (DP) || Load accumulator with RAM content pointed by DP ||  
 
|-
 
|-
−
| LM || || 1 ||  
+
| LM || 38 + D[1:0] || 1 || 1 || A<sub>CC</sub> ← (DP)<br />DP<sub>H</sub> ← DP<sub>H</sub> ^ D[1:0] || Load accumulator with RAM content pointed by DP;<br />Exclusive-or DP<sub>H</sub> with immediate data D[1:0] ||
 
|-
 
|-
−
| X || || 1 ||  
+
| X || 28 || 1 || 1 || A<sub>CC</sub> ↔ (DP) || Exchange accumulator with RAM content pointed by DP ||  
 
|-
 
|-
−
| XM || || 1 ||  
+
| XM || 28 + D[1:0] || 1 || 1 || A<sub>CC</sub> ↔ (DP)<br />DP<sub>H</sub> ← DP<sub>H</sub> ^ D[1:0] || Exchange accumulator with RAM content pointed by DP;<br />Exclusive-or DP<sub>H</sub> with immediate data D[1:0] ||  
 
|-
 
|-
−
| XD || || 1 ||  
+
| XD || 2C || 1 || 1 + skip || || ||
 
|-
 
|-
−
| XMD || || 1 ||  
+
| XMD || 2C + D[1:0] || 1 || 1 + skip || || ||
 
|-
 
|-
−
| XI || || 1 ||  
+
| XI || 3C || 1 || 1 + skip || || ||  
 
|-
 
|-
−
| XMI || || 1 ||  
+
| XMI || 3C + D[1:0] || 1 || 1 + skip || || ||
 
|-
 
|-
−
| LDI || || 2 ||  
+
| LDI || 15 00 + D[6:0] || 2 || 2 || || ||  
 
|-
 
|-
−
| LDZ || || 1 ||  
+
| LDZ || 80 + D[3:0] || 1 || 1 || || ||  
 
|-
 
|-
−
| DED || || 1 ||  
+
| DED || 13 || 1 || 1 + skip || || ||  
 
|-
 
|-
−
| IND || || 1 ||  
+
| IND || 33 || 1 || 1 + skip || || ||
 
|-
 
|-
−
| TAL || || 1 ||  
+
| TAL || 07 || 1 || 1 || || ||
 
|-
 
|-
−
| TLA || || 1 ||  
+
| TLA || 12 || 1 || 1 || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| XHX || || 1 ||  
+
| XHX || 4F || 1 ||  2 || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| XLY || || 1 ||  
+
| XLY || 4E || 1 ||  2 || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| THX || || 1 ||  
+
| THX || 47 || 1 ||  2 || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| TLY || || 1 ||  
+
| TLY || 46 || 1 || 2 || || || 
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| XAZ || || 1 ||  
+
| XAZ || 4A || 1 || 2 || || || 
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| XAW || || 1 ||  
+
| XAW || 4B || 1 || 2 || || || 
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| TAZ || || 1 ||  
+
| TAZ || 42 || 1 ||  2 || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| TAW || || 1 ||  
+
| TAW || 43 || 1 ||  2 || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| XHR || || 1 ||  
+
| XHR || 4D || 1 || 2 || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| XLS || || 1 ||  
+
| XLS || 4C || 1 || 2 || || || 
 
|-
 
|-
−
| SMB || || 1 ||  
+
| SMB || 78 + D[1:0] || 1 || 1 || || ||
 
|-
 
|-
−
| RMB || || 1 ||  
+
| RMB || 68 + D[1:0] || 1 || 1 || || ||
 
|-
 
|-
−
| TMB || || 1 ||  
+
| TMB || 58 + D[1:0] || 1 || 1 + skip || || ||  
 
|-
 
|-
−
| TAB || || 1 ||  
+
| TAB || 24 + D[1:0] || 1 || 1 + skip || || ||  
 
|-
 
|-
−
| CMB || || 1 ||  
+
| CMB || 34 + D[1:0] || 1 || 1 + skip || || ||  
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| SFB || || 1 ||  
+
| SFB || 7C + D[1:0] || 1 || 2 || || ||
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| RFB || || 1 ||  
+
| RFB || 6C + D[1:0] || 1 || 2 || || ||
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| FBT || || 1 ||  
+
| FBT || 5C + D[1:0] || 1 || 2 + skip || || ||
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| FBF || || 1 ||  
+
| FBF || 20 + D[1:0] || 1 || 2 + skip || || ||
 
|-
 
|-
−
| CM || || 1 ||  
+
| CM || 0C || 1 || 1 + skip || || || 
 
|-
 
|-
−
| CI || || 2 ||  
+
| CI || 17 C0 + D[3:0] || 2 || 2 + skip || || ||  
 
|-
 
|-
−
| CLI || || 2 ||  
+
| CLI || 16 E0 + D[3:0] || 2 || 2 + skip || || ||
 
|-
 
|-
−
| TC || || 1 ||  
+
| TC || 04 || 1 || 1 + skip || || ||  
 
|-
 
|-
−
| TIT || || 1 ||  
+
| TIT || 03 || 1 || 1 + skip || || ||
 
|-
 
|-
−
| JCP || || 1 ||  
+
| JCP || C0 + D[5:0] || 1 || 1 || || ||
 
|-
 
|-
−
| JMP || || 2 ||  
+
| JMP || A0 + D[10:8]<br /> 00 + D[7:0] || 2 || 2 || || ||  
 
|-
 
|-
−
| JPA || || 1 ||  
+
| JPA || 41 || 1 || 2 || || || 
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| EI || || 1 ||  
+
| EI || 31 || 1 || 1 || || ||
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| DI || || 1 ||  
+
| DI || 01 || 1 || 1 || || ||  
 
|-
 
|-
−
| CZP || || 1 ||  
+
| CZP || B0 + D[3:0] || 1 || 1 || || ||
 
|-
 
|-
−
| CAL || || 2 ||  
+
| CAL || A8 + D[10:8]<br /> 00 + D[7:0] || 2 || 2 || || ||  
 
|-
 
|-
−
| RT || || 1 ||  
+
| RT || 48 || 1 || 2 ||
 
|-
 
|-
−
| RTS || || 1 ||  
+
| RTS || 49 || 1 || 2 + skip || || ||
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| STM || || 2 ||  
+
| STM || 14 80 + D[5:0] || 2 || 2 || || || 
−
|- style="background: #ccffcc;"
+
|- style="background: #cfc;"
−
| TTM || || 1 ||  
+
| TTM || 05 || 1 || 1 + skip || || ||
 
|-
 
|-
−
| SEB || || 1 ||  
+
| SEB || 74 + D[1:0] || 1 || 2 || || ||
 
|-
 
|-
−
| REB || || 1 ||  
+
| REB || 64 + D[1:0] || 1 || 2 || || ||
 
|-
 
|-
−
| SPB || || 1 ||  
+
| SPB || 70 + D[1:0] || 1 || 1 || || ||  
 
|-
 
|-
−
| RPB || || 1 ||  
+
| RPB || 60 + D[1:0] || 1 || 1 || || ||
 
|-
 
|-
−
| TPA || || 1 ||  
+
| TPA || 54 + D[1:0] || 1 || 2 + skip || || ||
 
|-
 
|-
−
| TPB || || 1 ||  
+
| TPB || 50 + D[1:0] || 1 || 1 + skip || || ||  
 
|-
 
|-
−
| OE || || 1 ||  
+
| OE || 44 || 1 || 2 || || ||
 
|-
 
|-
−
| OP || || 1 ||  
+
| OP || 0E || 1 || 1 || || ||  
 
|-
 
|-
−
| OCD || || 2 || 2 || PORT[C,D] ← I<sub>7</sub>-I<sub>0</sub> ||
+
| OCD || 1E 00 + D[7:0] || 2 || 2 || PORT[C,D] ← I<sub>7</sub>-I<sub>0</sub> || ||
 
|-
 
|-
−
| IA || || 2 || 2 || A<sub>CC</sub> ← PORT[A] ||
+
| IA || 40 || 1 || 2 || A<sub>CC</sub> ← PORT[A] || ||
 
|-
 
|-
−
| IP || || 1 || 1 || A<sub>CC</sub> ← PORT[DP<sub>L</sub>] ||
+
| IP || 32 || 1 || 1 || A<sub>CC</sub> ← PORT[DP<sub>L</sub>] || ||
 
|-
 
|-
−
| [[NOP]] || || 1 || 1 || [[no operation]] ||
+
| [[NOP]] || 00 || 1 || 1 || [[no operation]] || ||
 
|}
 
|}
  
Line 184: Line 184:
 
* [[:File:NEC μCOM4345 ISA.pdf|ISA data sheet]]
 
* [[:File:NEC μCOM4345 ISA.pdf|ISA data sheet]]
  
 +
== References ==
 +
*NEC Electronics (Europe) GmbH, 1982 Catalog, "μCOM-4: 4-Bit Single Chip Microcomputer Family", 143-176 pp.
 +
 
== See also ==
 
== See also ==
 
* {{nec|μCOM-4}}
 
* {{nec|μCOM-4}}
 
* {{nec|μCOM-8}}
 
* {{nec|μCOM-8}}
 
* {{nec|μCOM-8/isa|μCOM-8 ISA}}
 
* {{nec|μCOM-8/isa|μCOM-8 ISA}}

Latest revision as of 13:27, 29 October 2023

The μCOM-4 ISA was an instruction set architecture composed of 80 instructions that were implemented by the NEC in their μCOM-4 family of microcontrollers. The μCOM-43 family implemented the complete ISA, while the μCOM-44 and μCOM-45 families implemented a strict subset of it. (Note that the μCOM-42 family had its own instruction set.)

Block diagram[edit]

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Registers[edit]

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Features[edit]

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Instructions[edit]

The μCOM-43 has support for all 80 instructions. The μCOM-44/μCOM-45 support a strict subset of it composed of 58 instruction. The majority of those 22 instructions deal with the added features only found in the μCOM-43 models.

Mnemonic OPCode Bytes Cycles Function Meaning Skip Condition
CLA 90 1 1 ACC ← 0 Clear accumulator
CMA 10 1 1 ACC ← ~ACC 1-s complement accumulator
CIA 11 1 1 ACC ← ~ACC + 1 2-s complement accumulator
INC 0D 1 1 + skip ACC ← ACC + 1 Increment accumulator, skip if overflow on overflow
DEC 0F 1 1 + skip ACC ← ACC - 1 Decrement accumulator, skip if underflow on underflow
CLC 0B 1 1 C ← 0 Clear carry flag
STC 1B 1 1 C ← 1 Set carry flag
XC 1A 1 1 C ↔ C' Exchange carry flag with carry save
RAR 30 1 1 C → ACC → C Rotate accumulator right through carry flag
INM 1D 1 1 + skip (DP) = (DP) + 1 Increment RAM content pointed by DP, skip if result is zero on (DP) = 0
DEM 1F 1 1 + skip (DP) = (DP) - 1 Decrement RAM content pointed by DP, skip if result is 0Fh on (DP) = 0Fh
AD 08 1 1 + skip ACC ← ACC + (DP) Add RAM content pointed by DP to accumulator, skip if overflow on overflow
ADS 09 1 1 + skip ACC ← ACC + (DP) + C
C ← 1 on overflow 		Add RAM content pointed by DP with carry to accumulator
If overflow set carry flag and skip 		on overflow
ADC 19 1 1 ACC ← ACC + (DP) + C
C ← 1 on overflow 		Add RAM content pointed by DP with carry to accumulator
If overflow set carry flag
DAA 06 1 1 ACC ← ACC + 6 Decimal adjust accumulator for BCD addition
DAS 0A 1 1 ACC ← ACC + 10 Decimal adjust accumulator for BCD subtraction
EXL 18 1 1 ACC ← ACC ^ (DP) Exclusive-or accumulator with RAM content pointed by DP
LI 90 + D[3:0] 1 1 ACC ← D[3:0] Load accumulator with immediate data D[3:0]
S 02 1 1 (DP) ← ACC Store accumulator into RAM location pointed by DP
L 38 1 1 ACC ← (DP) Load accumulator with RAM content pointed by DP
LM 38 + D[1:0] 1 1 ACC ← (DP)
DPH ← DPH ^ D[1:0] 		Load accumulator with RAM content pointed by DP;
Exclusive-or DPH with immediate data D[1:0]
X 28 1 1 ACC ↔ (DP) Exchange accumulator with RAM content pointed by DP
XM 28 + D[1:0] 1 1 ACC ↔ (DP)
DPH ← DPH ^ D[1:0] 		Exchange accumulator with RAM content pointed by DP;
Exclusive-or DPH with immediate data D[1:0]
XD 2C 1 1 + skip
XMD 2C + D[1:0] 1 1 + skip
XI 3C 1 1 + skip
XMI 3C + D[1:0] 1 1 + skip
LDI 15 00 + D[6:0] 2 2
LDZ 80 + D[3:0] 1 1
DED 13 1 1 + skip
IND 33 1 1 + skip
TAL 07 1 1
TLA 12 1 1
XHX 4F 1 2
XLY 4E 1 2
THX 47 1 2
TLY 46 1 2
XAZ 4A 1 2
XAW 4B 1 2
TAZ 42 1 2
TAW 43 1 2
XHR 4D 1 2
XLS 4C 1 2
SMB 78 + D[1:0] 1 1
RMB 68 + D[1:0] 1 1
TMB 58 + D[1:0] 1 1 + skip
TAB 24 + D[1:0] 1 1 + skip
CMB 34 + D[1:0] 1 1 + skip
SFB 7C + D[1:0] 1 2
RFB 6C + D[1:0] 1 2
FBT 5C + D[1:0] 1 2 + skip
FBF 20 + D[1:0] 1 2 + skip
CM 0C 1 1 + skip
CI 17 C0 + D[3:0] 2 2 + skip
CLI 16 E0 + D[3:0] 2 2 + skip
TC 04 1 1 + skip
TIT 03 1 1 + skip
JCP C0 + D[5:0] 1 1
JMP A0 + D[10:8]
00 + D[7:0] 		2 2
JPA 41 1 2
EI 31 1 1
DI 01 1 1
CZP B0 + D[3:0] 1 1
CAL A8 + D[10:8]
00 + D[7:0] 		2 2
RT 48 1 2
RTS 49 1 2 + skip
STM 14 80 + D[5:0] 2 2
TTM 05 1 1 + skip
SEB 74 + D[1:0] 1 2
REB 64 + D[1:0] 1 2
SPB 70 + D[1:0] 1 1
RPB 60 + D[1:0] 1 1
TPA 54 + D[1:0] 1 2 + skip
TPB 50 + D[1:0] 1 1 + skip
OE 44 1 2
OP 0E 1 1
OCD 1E 00 + D[7:0] 2 2 PORT[C,D] ← I7-I0
IA 40 1 2 ACC ← PORT[A]
IP 32 1 1 ACC ← PORT[DPL]
NOP 00 1 1 no operation

  - μCOM-43 only

Documents[edit]

References[edit]

  • NEC Electronics (Europe) GmbH, 1982 Catalog, "μCOM-4: 4-Bit Single Chip Microcomputer Family", 143-176 pp.

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=nec/μcom-4/isa&oldid=101958"