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{{intel title|Hyper Scaling}}
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#REDIRECT [[10_nm_lithography_process#Intel]]
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'''Hyper Scaling''' is an umbrella marketing term used by [[Intel]] to describe a collection of [[scaling boosters]] used in the [[fabrication process]] of extremely high-density CMOS logic, starting with their [[10 nm]] [[technology node|node]].
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== Overview ==
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For their [[10 nm lithography process]], Intel aimed at a 2.7x transistor compaction ratio over their [[14 nm node]], the highest density jump ever attempted between two consecutive [[technology nodes]] in the [[semiconductor industry]]. In order to reach such density increase, Intel had to resort to additional [[scaling boosters]] beyond traditional scaling nobs such as the [[gate pitch]] and [[cell height]]. While not all the boosters are unique to Intel, their 10nm process was the first high-volume manufacturing process to incorporate all those enablers at once.
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Hyper Scaling incorporates the following technologies:
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* [[self-aligned quad patterning]] (SAQP)
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* [[single dummy gate]] (SDG)
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* [[self-aligned diffusion contacts]]
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** [[contact over active gate]] (COAG)
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The scaling boosters affect both the width and height of the cells. When introduced at their [[10 nm]] node, Intel reported a cell height reduction of 10% for the introduction of COAG in for the width of the cells, Intel reported a 20% reduction in cell area for moving to a [[single diffusion break|SDB]].
