Semiconductor & Computer Engineering
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Difference between revisions of "Template:packaging"
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| − | < | + | <table class="guidebox"> |
| − | < | + | <tr><td colspan="2">{{Navbar|Template:packaging|text=|mini=1|style=float:left;}}</td></tr> |
| − | < | + | <tr><td class="header-main" colspan="2">Packaging</td></tr> |
| + | <tr><td colspan="2" style="text-align: center;">[[File:wc 3d stack.svg|225px|link=3d integration]]</td></tr> | ||
| + | <tr><td class="header" colspan="2">Technologies</td></tr> | ||
| + | <tr><td colspan="2"> | ||
* [[Wire bonding]] | * [[Wire bonding]] | ||
| + | * [[thruchip interface|TCI]] | ||
* [[through-silicon via|TSV]] | * [[through-silicon via|TSV]] | ||
| − | * [[ | + | * [[through-glass via|TGV]] |
| − | < | + | * [[face-to-face|F2F]] |
| − | * [[ | + | * [[flip chip|FC]] |
| − | * [[ | + | </td></tr> |
| − | * [[2. | + | <tr><td class="header" colspan="2">Concepts</td></tr> |
| − | {{ | + | <tr><td colspan="2"> |
| − | </ | + | * [[Chip-on-Board|COB]] |
| + | * [[Chip-Scale Package|CSP]] | ||
| + | * [[Package-in-Package|PiP]] | ||
| + | * [[System-in-Package|SiP]] | ||
| + | * [[Package-on-Package|PoP]] | ||
| + | </td></tr> | ||
| + | <tr><td class="header" colspan="2">Single-Row</td></tr> | ||
| + | <tr><td colspan="2"> | ||
| + | * [[single in-line package|SiP]] | ||
| + | </td></tr> | ||
| + | <tr><td class="header" colspan="2">Dual-Row</td></tr> | ||
| + | <tr><td colspan="2"> | ||
| + | * [[dual in-line package|DIP]] | ||
| + | * [[dual-flat no-leads|DFN]] | ||
| + | * [[small outline integrated circuit|SOIC]] | ||
| + | * [[thin small outline package|TSOP]] | ||
| + | * [[zig-zag in-line package|ZIP]] | ||
| + | </td></tr> | ||
| + | <tr><td class="header" colspan="2">Quad-Row</td></tr> | ||
| + | <tr><td colspan="2"> | ||
| + | * [[quad-flat no-leads|QFN]] | ||
| + | </td></tr> | ||
| + | <tr><td class="header" colspan="2">Grid Array</td></tr> | ||
| + | <tr><td colspan="2"> | ||
| + | * [[ball grid array|BGA]] | ||
| + | * [[land grid array|LGA]] | ||
| + | * [[pin grid array|PGA]] | ||
| + | </td></tr> | ||
| + | <tr><td class="header" colspan="2">2.5D IC</td></tr> | ||
| + | <tr><td colspan="2"> | ||
| + | * [[2.5D IC]] | ||
| + | * [[Interposer]] | ||
| + | * [[Embedded Interposer]] | ||
| + | * [[Embedded Bridge]] | ||
| + | * {{tsmc|CoWoS}} | ||
| + | * {{intel|EMIB}} | ||
| + | </td></tr> | ||
| + | <tr><td class="header" colspan="2">3D IC</td></tr> | ||
| + | <tr><td colspan="2"> | ||
| + | * [[3D IC]] | ||
| + | * {{intel|Foveros}} | ||
| + | * {{tsmc|WoW}} | ||
| + | * {{tsmc|SoIC}} | ||
| + | </td></tr> | ||
| + | </table> | ||
Latest revision as of 00:30, 25 December 2018
| Packaging | |
 | |
| Technologies | |
| Concepts | |
| Single-Row | |
| Dual-Row | |
| Quad-Row | |
| Grid Array | |
| 2.5D IC | |
| 3D IC | |