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Difference between revisions of "amd/epyc/7251"
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{{amd title|EPYC 7251}} | {{amd title|EPYC 7251}} | ||
{{chip | {{chip | ||
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|name=EPYC 7251 | |name=EPYC 7251 | ||
|no image=Yes | |no image=Yes | ||
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|model number=7251 | |model number=7251 | ||
|part number=PS7251BFV8SAF | |part number=PS7251BFV8SAF | ||
+ | |part number 2=PS7251BFAFWOF | ||
|market=Server | |market=Server | ||
|first announced=June 20, 2017 | |first announced=June 20, 2017 | ||
+ | |first launched=June 20, 2017 | ||
+ | |release price=$574 | ||
|family=EPYC | |family=EPYC | ||
|series=7000 | |series=7000 | ||
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|max memory=2 TiB | |max memory=2 TiB | ||
|tdp=120 W | |tdp=120 W | ||
− | |package | + | |tcase min=0 °C |
+ | |tcase max=81 °C | ||
+ | |package name 1=amd,socket_sp3 | ||
}} | }} | ||
'''EPYC 7251''' is a dual-socket {{arch|64}} [[octa-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7251 has a base frequency of 2.1 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 120 W and supports up to 2 TiB of octa-channel DDR4-2400 ECC memory per socket. | '''EPYC 7251''' is a dual-socket {{arch|64}} [[octa-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7251 has a base frequency of 2.1 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 120 W and supports up to 2 TiB of octa-channel DDR4-2400 ECC memory per socket. |
Latest revision as of 11:36, 18 March 2023
Edit Values | |
EPYC 7251 | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 7251 |
Part Number | PS7251BFV8SAF, PS7251BFAFWOF |
Market | Server |
Introduction | June 20, 2017 (announced) June 20, 2017 (launched) |
Release Price | $574 |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7000 |
Locked | No |
Frequency | 2,100 MHz |
Turbo Frequency | 2,900 MHz (1 core), 2,900 MHz (2 cores), 2,900 MHz (3 cores), 2,900 MHz (4 cores), 2,900 MHz (5 cores), 2,900 MHz (6 cores), 2,900 MHz (7 cores), 2,900 MHz (8 cores) |
Clock multiplier | 21 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen |
Core Name | Naples |
Core Family | 23 |
Core Model | 1 |
Core Stepping | B2 |
Process | 14 nm |
Transistors | 19,200,000,000 |
Technology | CMOS |
Die | 213 mm² |
MCP | Yes (4 dies) |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 120 W |
Tcase | 0 °C – 81 °C |
Packaging | |
Package | SP3, FCLGA-4094 (FC-OLGA) |
Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
Pitch | 0.87 mm × 1 mm |
Contacts | 4094 |
Socket | SP3, LGA-4094 |
EPYC 7251 is a dual-socket 64-bit octa-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7251 has a base frequency of 2.1 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 120 W and supports up to 2 TiB of octa-channel DDR4-2400 ECC memory per socket.
Contents
Cache[edit]
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 286.2 GiB/s.
Expansions[edit]
The EPYC 7351P has 128 Gen 3 PCIe lanes.
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Facts about "EPYC 7251 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7251 - AMD#io + |
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
clock multiplier | 21 + |
core count | 8 + |
core family | 23 + |
core model | 1 + |
core name | Naples + |
core stepping | B2 + |
designer | AMD + |
die area | 213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) + |
die count | 4 + |
family | EPYC + |
first announced | June 20, 2017 + |
full page name | amd/epyc/7251 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | false + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | 3000 + |
manufacturer | GlobalFoundries + |
market segment | Server + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 143.1 GiB/s (146,534.4 MiB/s, 153.652 GB/s, 153,652.455 MB/s, 0.14 TiB/s, 0.154 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 128 + |
microarchitecture | Zen + |
model number | 7251 + |
name | EPYC 7251 + |
part number | PS7251BFV8SAF + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 574.00 (€ 516.60, £ 464.94, ¥ 59,311.42) + |
series | 7000 + |
smp max ways | 2 + |
supported memory type | DDR4-2400 + |
tdp | 120 W (120,000 mW, 0.161 hp, 0.12 kW) + |
technology | CMOS + |
thread count | 16 + |
transistor count | 19,200,000,000 + |
turbo frequency (1 core) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (2 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (3 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (4 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (5 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (6 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (7 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (8 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |