Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon e5/e5-2630 v4"
m (Bot: replacing deprecated (and now obselete) {{mpu features}} with {{x86 features}}) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{intel title|Xeon E5-2630 v4}} | {{intel title|Xeon E5-2630 v4}} | ||
| − | {{ | + | {{chip |
| name = Xeon E5-2630 v4 | | name = Xeon E5-2630 v4 | ||
| no image = Yes | | no image = Yes | ||
| Line 134: | Line 134: | ||
== Expansions == | == Expansions == | ||
| − | {{ | + | {{expansions |
| pcie revision = 3.0 | | pcie revision = 3.0 | ||
| pcie lanes = 40 | | pcie lanes = 40 | ||
Latest revision as of 15:27, 13 December 2017
| Edit Values | |
| Xeon E5-2630 v4 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | E5-2630 v4 |
| Part Number | CM8066002032301, BX80660E52630V4 |
| S-Spec | SR2R7 QKET (QS) |
| Market | Server |
| Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
| Release Price | $667.00 |
| Shop | Amazon |
| General Specs | |
| Family | Xeon E5 |
| Series | E5-2000 |
| Locked | Yes |
| Frequency | 2,200 MHz |
| Turbo Frequency | Yes |
| Turbo Frequency | 3,100 MHz (1 core), 3,100 MHz (2 cores), 2,900 MHz (3 cores), 2,800 MHz (4 cores), 2,700 MHz (5 cores), 2,600 MHz (6 cores), 2,500 MHz (7 cores), 2,400 MHz (8 cores), 2,400 MHz (9 cores), 2,400 MHz (10 cores) |
| Bus type | QPI |
| Bus speed | 4,000 MHz |
| Bus rate | 2 × 8 GT/s |
| Clock multiplier | 22 |
| CPUID | 406F1 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Broadwell |
| Platform | Grantley EP 2S |
| Chipset | C610 Series |
| Core Name | Broadwell EP |
| Core Family | 6 |
| Core Model | 4F |
| Core Stepping | R0 |
| Process | 14 nm |
| Transistors | 3,200,000,000 |
| Technology | CMOS |
| Die | 246.24 mm² |
| Word Size | 64 bit |
| Cores | 10 |
| Threads | 20 |
| Max Memory | 1,536 GiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
| Electrical | |
| Vcore | 1.82 V |
| VI/O | 1.2 V ± 3% |
| TDP | 85 W |
| Tcase | 0 °C – 74 °C |
| Tstorage | -25 °C – 125 °C |
The Xeon E5-2630 v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for standard 2S environments (1U square form factor). Operating at 2.2 GHz with a turbo boost frequency of 3.1 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a 14 nm process (based on Broadwell).
Cache[edit]
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 2.5 MiB 2,560 KiB 2,621,440 B 0.00244 GiB |
10x256 KiB 8-way set associative (per core, write-back) |
| L3$ | 25 MiB 25,600 KiB 26,214,400 B 0.0244 GiB |
10x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR4-2133 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max bandwidth | 63.58 GiB/s |
| Bandwidth (single) | 15.89 GiB/s |
| Bandwidth (dual) | 31.79 GiB/s |
| Max memory | 1,536 GiB |
| Physical Address Extensions | 46 bit |
Expansions[edit]
 |
Expansion Options
|
|||||||
|
||||||||
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||||||||||||||||||||||||
|
||||||||||||||||||||||||||||||||||||||||
Facts about "Xeon E5-2630 v4 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-2630 v4 - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions + |
| has intel enhanced speedstep technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
| l3$ description | 20-way set associative + |
| l3$ size | 25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) + |
| max pcie lanes | 40 + |