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Difference between revisions of "intel/xeon e5/e5-1680 v4"
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{{intel title|Xeon E5-1680 v4}}
 
{{intel title|Xeon E5-1680 v4}}
−
{{mpu
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{{chip
 
| name                = Xeon E5-1680 v4
 
| name                = Xeon E5-1680 v4
 
| no image            = Yes
 
| no image            = Yes
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== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 3.0
 
| pcie revision      = 3.0
 
| pcie lanes        = 40
 
| pcie lanes        = 40
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== Features ==  
 
== Features ==  
 
{{x86 features
 
{{x86 features
−
| em64t      = Yes
+
|real=No
−
| nx          = Yes
+
|protected=No
−
| txt        = Yes
+
|smm=No
−
| tsx        = Yes
+
|fpu=No
−
| vpro        = Yes
+
|x8616=No
−
| ht          = Yes
+
|x8632=No
−
| tbt1        =  
+
|x8664=No
−
| tbt2        = Yes
+
|nx=Yes
−
| tbmt3      = Yes
+
|mmx=Yes
−
| bpt        =  
+
|emmx=No
−
| vt-x        = Yes
+
|sse=Yes
−
| vt-d        = Yes
+
|sse2=Yes
−
| ept        = Yes
+
|sse3=Yes
−
| mmx        = Yes
+
|ssse3=Yes
−
| sse        = Yes
+
|sse41=No
−
| sse2        = Yes
+
|sse42=No
−
| sse3        = Yes
+
|sse4a=No
−
| ssse3      = Yes
+
|avx=Yes
−
| sse4.1      = Yes
+
|avx2=Yes
−
| sse4.2      = Yes
+
|avx512f=No
−
| aes        = Yes
+
|avx512cd=No
−
| pclmul      = Yes
+
|avx512er=No
−
| avx        = Yes
+
|avx512pf=No
−
| avx2        = Yes
+
|avx512bw=No
−
| bmi        = Yes
+
|avx512dq=No
−
| bmi1        = Yes
+
|avx512vl=No
−
| bmi2        = Yes
+
|avx512ifma=No
−
| f16c        = Yes
+
|avx512vbmi=No
−
| fma3        = Yes
+
|avx5124fmaps=No
−
| mpx        =  
+
|avx5124vnniw=No
−
| sgx        =  
+
|avx512vpopcntdq=No
−
| eist        = Yes
+
|abm=No
−
| secure key = Yes
+
|tbm=No
−
| os guard   = Yes
+
|bmi1=Yes
−
| intel at    =
+
|bmi2=Yes
−
| intel ipt   = Yes
+
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=No
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|em64t=Yes
 +
|vt-x=Yes
 +
|vt-d=Yes
 +
|sse4_1=Yes
 +
|sse4_2=Yes
 +
|pclmul=Yes
 +
|bmi=Yes
 +
|secure key=Yes
 +
|os guard=Yes
 +
|intel ipt=Yes
 
}}
 
}}

Latest revision as of 00:04, 24 December 2017

Edit Values
Xeon E5-1680 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-1680 v4
Part NumberCM8066002044401
S-SpecSR2P8
QKF3 (QS), QKVM (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$1723.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-1000
LockedYes
Frequency3,400 MHz
Turbo FrequencyYes
Turbo Frequency4,000 MHz (1 core)
Bus typeDMI 2.0
Bus rate5 GT/s
Clock multiplier34
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP Workstation
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores8
Threads16
Max Memory1,536 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP140 W
Tcase0 °C – 70 °C
Tstorage-25 °C – 125 °C

The Xeon E5-1680 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 1S workstations. Operating at 3.4 GHz with a turbo boost frequency of 4 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8x256 KiB 8-way set associative (per core, write-back)
L3$ 20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
8x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-1680_v4&oldid=71480"
Facts about "Xeon E5-1680 v4 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-1680 v4 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Turbo Boost Max Technology 3.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost max technology 3 0true +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description20-way set associative +
l3$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
max pcie lanes40 +