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Difference between revisions of "amd/k6-2/k6-2-500ack"
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Latest revision as of 15:08, 13 December 2017

Edit Values
K6-2/500ACK
General Info
DesignerAMD
ManufacturerAMD
Model NumberK6-2/500ACK
Part NumberAMD-K6-2/500ACK
MarketMobile
IntroductionSeptember 20, 1999 (announced)
September 20, 1999 (launched)
ShopAmazon
General Specs
FamilyK6-2
SeriesK6-2 Mobile P
Frequency499.99 MHz
Bus typeFSB
Bus speed99.99 MHz
Bus rate99.99 MT/s
Clock multiplier5
CPUID58C
Microarchitecture
MicroarchitectureK6-2
PlatformSuper 7
Core NameChomper Extended
Core Family5
Core Model8
Core Stepping12
Process0.25 µm
Transistors9,300,000
TechnologyCMOS
Die81 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore2.0 V ± 0.1 V
VI/O3.3675 V ± 7%
Tcase0 °C – 80 °C
Tstorage-65 °C – 150 °C

K6-2/500ACK was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 500 MHz with a FSB operating at 100 MHz.

Cache[edit]

Main article: K6-2 § Cache

L2$ can be 512 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative

Graphics[edit]

This SoC has no integrated graphics processing unit.

Features[edit]

  • Auto-power down state
  • Stop clock state

Documents[edit]

DataSheet[edit]

Facts about "K6-2/500ACK - AMD"
l1d$ description2-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +