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Difference between revisions of "sun microsystems/ultrasparc/stp1030bga-200"
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{{sun title|UltraSPARC-I 200MHz}}
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|name=UltraSPARC-I 200MHz
 
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'''UltraSPARC-I 200MHz''' was a {{arch|64}} [[SPARC]] microprocessor designed and introduced by [[Sun Microsystems]] in [[1996]].
 
'''UltraSPARC-I 200MHz''' was a {{arch|64}} [[SPARC]] microprocessor designed and introduced by [[Sun Microsystems]] in [[1996]].
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== Cache ==
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{{main|sun microsystems/microarchitectures/ultrasparc-i#Memory_Hierarchy|l1=UltraSPARC-I § Cache}}
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In addition to the on-chip cache, this chip also required an external cache that is either 512 KiB, 1 MiB, 2 MiB, or 4 MiB with a line size of 64 bytes.
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{{cache size
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|l1 cache=32 KiB
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|l1i cache=16 KiB
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|l1i break=1x16 KiB
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|l1i desc=2-way set associative
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|l1d cache=16 KiB
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|l1d break=1x16 KiB
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|l1d desc=16-way set associative
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|l1d policy=write-through
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}}
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== Documents ==
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=== Datasheets ===
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* [[:File:stp1030a.pdf|UltraSPARC-I High-Performance, 167 & 200 MHz, 64-bit RISC Processor Datasheet]], October 1996

Latest revision as of 16:32, 13 December 2017

Edit Values
UltraSPARC-I 200MHz
Ic-photo-Sun--STP1030ABGA-200--(UltraSPARC-CPU).JPG
General Info
DesignerSun Microsystems
ManufacturerTexas Instruments
Model NumberUltraSPARC-I 200MHz
Part NumberSTP103OBGA-200
MarketServer, Workstation
Introduction1996 (announced)
1996 (launched)
General Specs
FamilyUltraSPARC
SeriesUltraSPARC-I
Frequency200 MHz
Microarchitecture
ISASPARC V9 (SPARC)
MicroarchitectureUltraSPARC-I
Process0.5 µm
Transistors5,200,000
TechnologyCMOS
Die310 mm²
Word Size64 bit
Cores1
Threads1
Electrical
Vcore3.3 V
Packaging
PackageBGA-521 (BGA)UltraSPARC-I package back.png
Pins521

UltraSPARC-I 200MHz was a 64-bit SPARC microprocessor designed and introduced by Sun Microsystems in 1996.

Cache[edit]

Main article: UltraSPARC-I § Cache

In addition to the on-chip cache, this chip also required an external cache that is either 512 KiB, 1 MiB, 2 MiB, or 4 MiB with a line size of 64 bytes.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
32,768 B
0.0313 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1x16 KiB2-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
1x16 KiB16-way set associativewrite-through

Documents[edit]

Datasheets[edit]

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Facts about "UltraSPARC-I 200MHz - Sun Microsystems"
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l1$ size32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description16-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description2-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +