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Difference between revisions of "qualcomm/microarchitectures/saphira"
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(Saphira supports ARMv8.4 (https://reviews.llvm.org/rL345827)) |
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{{qualcomm title|Saphira|arch}} | {{qualcomm title|Saphira|arch}} | ||
+ | {{microarchitecture | ||
+ | |atype=CPU | ||
+ | |name=Saphira | ||
+ | |designer=Qualcomm | ||
+ | |manufacturer=Samsung | ||
+ | |type=Superscalar | ||
+ | |type 2=Superpipeline | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
+ | |stages min=10 | ||
+ | |stages max=15 | ||
+ | |decode=4-way | ||
+ | |isa=ARMv8.4 | ||
+ | |feature=AArch64 | ||
+ | |extension=Hypervisor (EL2) | ||
+ | |extension 2=TrustZone (EL3) | ||
+ | |extension 3=NEON | ||
+ | |extension 4=CRC32 | ||
+ | |extension 5=Crypto | ||
+ | |extension 6=FP | ||
+ | |extension 7=RDM | ||
+ | |l1i=64 KiB | ||
+ | |l1i per=core | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d=32 KiB | ||
+ | |l1d per=core | ||
+ | |l1d desc=8-way set associative | ||
+ | |l2=512 KiB | ||
+ | |l2 per=duplex | ||
+ | |l2 desc=8-way set associative | ||
+ | |l3=5 MiB | ||
+ | |l3 per=block | ||
+ | |l3 desc=20-way set associative | ||
+ | |predecessor=Falkor | ||
+ | |predecessor link=qualcomm/microarchitectures/falkor | ||
+ | |inst=Yes | ||
+ | }} | ||
'''Saphira''' is [[Qualcomm]]'s successor to {{\\|Falkor}}, an [[ARM]] microarchitecture for the server market. | '''Saphira''' is [[Qualcomm]]'s successor to {{\\|Falkor}}, an [[ARM]] microarchitecture for the server market. | ||
+ | |||
+ | == Process Technology == | ||
+ | Qualcomm has not yet disclosed the process chosen for Saphira but it will most likely be on Samsung's [[8nm]] (DUV) or [[7nm]] (EUV). | ||
+ | |||
+ | == Release dates == | ||
+ | Qualcomm first disclosed Saphira at the official launch of the {{qualcomm|Centriq}} server family on November 8, 2017. | ||
+ | |||
+ | ==Architecture == | ||
+ | |||
+ | === Key changes from {{\\|Falkor}} === | ||
+ | {{future information}} | ||
+ | |||
+ | * ARMv8.3 (from ARMv8) |
Latest revision as of 18:12, 11 October 2019
Edit Values | |
Saphira µarch | |
General Info | |
Arch Type | CPU |
Designer | Qualcomm |
Manufacturer | Samsung |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 10-15 |
Decode | 4-way |
Instructions | |
ISA | ARMv8.4 |
Extensions | Hypervisor (EL2), TrustZone (EL3), NEON, CRC32, Crypto, FP, RDM |
Cache | |
L1I Cache | 64 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 512 KiB/duplex 8-way set associative |
L3 Cache | 5 MiB/block 20-way set associative |
Succession | |
Saphira is Qualcomm's successor to Falkor, an ARM microarchitecture for the server market.
Process Technology[edit]
Qualcomm has not yet disclosed the process chosen for Saphira but it will most likely be on Samsung's 8nm (DUV) or 7nm (EUV).
Release dates[edit]
Qualcomm first disclosed Saphira at the official launch of the Centriq server family on November 8, 2017.
Architecture[edit]
Key changes from Falkor[edit]
- ARMv8.3 (from ARMv8)
Facts about "Saphira - Microarchitectures - Qualcomm"
codename | Saphira + |
designer | Qualcomm + |
full page name | qualcomm/microarchitectures/saphira + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.4 + |
manufacturer | Samsung + |
microarchitecture type | CPU + |
name | Saphira + |
pipeline stages (max) | 15 + |
pipeline stages (min) | 10 + |