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Difference between revisions of "freescale/qoriq/p2020"
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{{freescale title|QorIQ P2020}}
 
{{freescale title|QorIQ P2020}}
−
{{mpu
+
{{chip
 
|name=P2020
 
|name=P2020
 
|no image=Yes
 
|no image=Yes
 
|designer=Freescale
 
|designer=Freescale
 
|manufacturer=IBM
 
|manufacturer=IBM
−
|model number=P1010
+
|model number=P2020
 
|market=Networking
 
|market=Networking
 
|market 2=Embedded
 
|market 2=Embedded
 
|first announced=June 16, 2008
 
|first announced=June 16, 2008
 
|first launched=2009
 
|first launched=2009
 +
|last order=2023
 
|family=QorIQ
 
|family=QorIQ
 
|series=P2
 
|series=P2
−
|frequency=1,200 MHz
+
|frequency=800 MHz
 +
|frequency 2=1,200 MHz
 +
|frequency 3=1,333 MHz
 
|isa=Power ISA v2.03
 
|isa=Power ISA v2.03
 
|isa family=Power
 
|isa family=Power
 
|microarch=e500
 
|microarch=e500
−
|core name=e500
+
|core name=e500 v2
 
|process=45 nm
 
|process=45 nm
 
|technology=CMOS
 
|technology=CMOS
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|core count=2
 
|core count=2
 
|thread count=2
 
|thread count=2
 +
|power=8 W
 
|tjunc min=0 °C
 
|tjunc min=0 °C
 
|tjunc max=125 °C
 
|tjunc max=125 °C
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
 
}}
 
}}
−
'''QorIQ P2020''' is a {{arch|32}} embedded [[dual-core]] [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 1.2 GHz and supports 64-bit DDR2/3 memory.
+
'''QorIQ P2020''' is a {{arch|32}} embedded [[dual-core]] [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 1.2 GHz and supports 64-bit DDR3-800 memory.
  
 
== Cache ==
 
== Cache ==
Line 65: Line 69:
 
* UART
 
* UART
 
* SEC 3.1 Security Acceleration
 
* SEC 3.1 Security Acceleration
 +
 +
== Block Diagram ==
 +
: [[File:qoriq p2010 block diagram.png|800px]]
 +
 +
== Documents ==
 +
* [[:File:QorIQ P2.pdf|QorIQ P2 Series Product Brief]]
 +
* [[:File:P2 Family App Bro.pdf|P2 Platform Series]]

Latest revision as of 12:29, 5 April 2020

Edit Values
P2020
General Info
DesignerFreescale
ManufacturerIBM
Model NumberP2020
MarketNetworking, Embedded
IntroductionJune 16, 2008 (announced)
2009 (launched)
End-of-life2023 (last order)
General Specs
FamilyQorIQ
SeriesP2
Frequency800 MHz, 1,200 MHz, 1,333 MHz
Microarchitecture
ISAPower ISA v2.03 (Power)
Microarchitecturee500
Core Namee500 v2
Process45 nm
TechnologyCMOS
Word Size32 bit
Cores2
Threads2
Electrical
Power dissipation8 W
Tjunction0 °C – 125 °C
Packaging
PackageTE-PBGA-II-689 (TE PBGA-II)
Temperature-Enhanced Plastic BGA
Dimension31 mm x 31 mm
Contacts689

QorIQ P2020 is a 32-bit embedded dual-core POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1.2 GHz and supports 64-bit DDR3-800 memory.

Cache[edit]

Main article: e500 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associativeWrite-through

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Controllers1
Channels1
Width64 bit
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 5.96 GiB/s

Expansions[edit]

  • 3x 10/100/1000 Eithernet with SGMII
  • 3x PCIe 1.0a controllers with 2 SerDes
  • 1x USB 2.0
  • SD/MMC
  • SPI
  • 2x I2C
  • UART
  • SEC 3.1 Security Acceleration

Block Diagram[edit]

qoriq p2010 block diagram.png

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=freescale/qoriq/p2020&oldid=96561"
Facts about "QorIQ P2020 - Freescale"
RDF feed
has ecc memory supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels1 +
supported memory typeDDR3-800 +