From WikiChip
Difference between revisions of "intel/celeron/797"
m (typo correction) |
|||
(6 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Celeron 797}} | {{intel title|Celeron 797}} | ||
− | {{ | + | {{chip |
|name=Celeron 797 | |name=Celeron 797 | ||
|no image=Yes | |no image=Yes | ||
Line 52: | Line 52: | ||
|package module 1={{packages/intel/fcbga-1023}} | |package module 1={{packages/intel/fcbga-1023}} | ||
}} | }} | ||
− | '''Celeron 797''' is a [[single-core]] budget mobile [[x86]] microprocessor introduced by [[Intel]] in early [[2012]]. The Celeron 797, which is based on the {{intel|Sandy Bridge|l=arch}} microarchitecture and is manufactured on a [[32 nm process]], operates at 1.4 GHz with a [[TDP]] of 17 W. This chip incorporates Intel's {{intel|HD Graphics (Sandy Bridge)|HD Graphics}} [[integrated graphics]] operating at 350 MHz with a | + | '''Celeron 797''' is a [[single-core]] budget mobile [[x86]] microprocessor introduced by [[Intel]] in early [[2012]]. The Celeron 797, which is based on the {{intel|Sandy Bridge|l=arch}} microarchitecture and is manufactured on a [[32 nm process]], operates at 1.4 GHz with a [[TDP]] of 17 W. This chip incorporates Intel's {{intel|HD Graphics (Sandy Bridge)|HD Graphics}} [[integrated graphics]] operating at 350 MHz with a burst frequency of 950 MHz. This processor supports 16 GiB of dual-channel DDR3-1333 memory. |
== Cache == | == Cache == | ||
Line 133: | Line 133: | ||
== Features == | == Features == | ||
− | {{x86 features}} | + | {{x86 features |
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=No | ||
+ | |avx2=No | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=No | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=Yes | ||
+ | |f16c=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=Yes | ||
+ | |fastmem=Yes | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Documents == | ||
+ | === Datasheet === | ||
+ | * [[:File:2nd-gen-core-family-mobile-vol-1-datasheet.pdf|Datasheet, Volume 1]] | ||
+ | * [[:File:2nd-gen-core-family-mobile-vol-2-datasheet.pdf|Datasheet, Volume 2]] | ||
+ | === Other === | ||
+ | * [[:File:2nd-gen-core-mobile-thermal-guide.pdf|Thermal Design Guide for Embedded Applications]] | ||
+ | * [[:File:2nd-gen-core-family-mobile-specification-update.pdf|2nd Gen Core Mobile Specification Update]] |
Latest revision as of 18:19, 17 March 2018
Edit Values | |||||||||
Celeron 797 | |||||||||
General Info | |||||||||
Designer | Intel | ||||||||
Manufacturer | Intel | ||||||||
Model Number | 797 | ||||||||
Part Number | AV8062701079601, AV8062701345500 | ||||||||
S-Spec | SR0ED, SR0VK | ||||||||
Market | Mobile | ||||||||
Introduction | January, 2012 (announced) January, 2012 (launched) | ||||||||
Release Price | $107 | ||||||||
Shop | Amazon | ||||||||
General Specs | |||||||||
Family | Celeron | ||||||||
Series | 700 | ||||||||
Locked | Yes | ||||||||
Frequency | 1,400 MHz | ||||||||
Bus type | DMI 2.0 | ||||||||
Bus rate | 4 × 5 GT/s | ||||||||
Clock multiplier | 14 | ||||||||
CPUID | 0x206A7 | ||||||||
Microarchitecture | |||||||||
ISA | x86-64 (x86) | ||||||||
Microarchitecture | Sandy Bridge | ||||||||
Platform | Sandy Bridge M | ||||||||
Chipset | Cougar Point | ||||||||
Core Name | Sandy Bridge M | ||||||||
Core Family | 6 | ||||||||
Core Model | 42 | ||||||||
Core Stepping | J1, Q0 | ||||||||
Process | 32 nm | ||||||||
Transistors | 504,000,000 | ||||||||
Technology | CMOS | ||||||||
Die | 131 mm² | ||||||||
Word Size | 64 bit | ||||||||
Cores | 1 | ||||||||
Threads | 1 | ||||||||
Max Memory | 16 GiB | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Electrical | |||||||||
Power (idle) | 2.3 W | ||||||||
Vcore | 0.3 V-1.52 V | ||||||||
TDP | 17 W | ||||||||
Tjunction | 0 °C – 100 °C | ||||||||
Tstorage | -25 °C – 125 °C | ||||||||
Packaging | |||||||||
|
Celeron 797 is a single-core budget mobile x86 microprocessor introduced by Intel in early 2012. The Celeron 797, which is based on the Sandy Bridge microarchitecture and is manufactured on a 32 nm process, operates at 1.4 GHz with a TDP of 17 W. This chip incorporates Intel's HD Graphics integrated graphics operating at 350 MHz with a burst frequency of 950 MHz. This processor supports 16 GiB of dual-channel DDR3-1333 memory.
Contents
Cache[edit]
- Main article: Sandy Bridge § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options |
|||||
|
Graphics[edit]
Integrated Graphics Information
|
|||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps |
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||
|
Documents[edit]
Datasheet[edit]
Other[edit]
Facts about "Celeron 797 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 797 - Intel#pcie + |
device id | 0x0106 + |
has ecc memory support | false + |
has feature | Intel VT-x + and Flex Memory Access + |
has intel flex memory access support | true + |
has intel vt-x technology | true + |
integrated gpu | HD Graphics (Sandy Bridge) + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 6 + |
integrated gpu max frequency | 950 MHz (0.95 GHz, 950,000 KHz) + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR3-1333 + and DDR3-1066 + |