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Difference between revisions of "intel/atom/c3558"
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{{intel title|Atom C3558}}
 
{{intel title|Atom C3558}}
−
{{mpu
+
{{chip
 
|name=Atom C3558
 
|name=Atom C3558
−
|no image=Yes
+
|image=denverton (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
Line 23: Line 23:
 
|core name=Denverton
 
|core name=Denverton
 
|core family=6
 
|core family=6
 +
|core model=95
 
|core stepping=B1
 
|core stepping=B1
 
|process=14 nm
 
|process=14 nm
Line 40: Line 41:
 
|package module 1={{packages/intel/fcbga-1310}}
 
|package module 1={{packages/intel/fcbga-1310}}
 
}}
 
}}
−
'''Atom C3558''' is a {{arch|64}} [[quad-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3558, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2.2 GHz with a [[TDP]] of 16 W. The C3558 supports up to a dual-channel of 256 GiB of DDR4-1866 [[ECC]] memory.
+
'''Atom C3558''' is a {{arch|64}} [[quad-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3558, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2.2 GHz with a [[TDP]] of 16 W. The C3558 supports up to 256 GiB of dual-channel DDR4-1866 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Network and Enterprise Storage SKUs]] and come with integrated {{intel|QuickAssist Technology}}.
  
 
== Cache ==
 
== Cache ==
Line 61: Line 62:
  
 
== Memory controller ==
 
== Memory controller ==
−
{{memory controller}}
+
{{memory controller
 +
|type=DDR3L-1600
 +
|type 2=DDR4-1866
 +
|ecc=Yes
 +
|max mem=256 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=27.82 GiB/s
 +
|bandwidth schan=13.91 GiB/s
 +
|bandwidth dchan=27.82 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
This chip incorporates 12 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=12
 +
|pcie config=x8
 +
|pcie config 2=x4
 +
|pcie config 3=x2
 +
|pcie config 4=x1
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=3.0
 +
|usb ports=8
 +
}}
 +
{{expansions entry
 +
|type=SATA
 +
|sata revision=3.0
 +
|sata ports=12
 +
}}
 +
{{expansions entry
 +
|type=HSIO
 +
|hsio lanes=12
 +
}}
 +
}}
 +
 
 +
== Networking ==
 +
{{network
 +
|eth opts=Yes
 +
|10ge=Yes
 +
|10ge ports=2
 +
|2.5ge=Yes
 +
|2.5ge ports=2
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 
 +
* Intel's Integrated {{intel|QuickAssist Technology}} supports a rate of up to 5 Gbps.

Latest revision as of 00:30, 15 August 2019

Edit Values
Atom C3558
denverton (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberC3558
Part NumberHW8076502639302
S-SpecSR388
MarketServer, Embedded
IntroductionAugust 15, 2017 (announced)
August 15, 2017 (launched)
Release Price$86.00
ShopAmazon
General Specs
FamilyAtom
Series3000
LockedYes
Frequency2,200 MHz
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureGoldmont
Core NameDenverton
Core Family6
Core Model95
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory256 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP16 W
Tjunction0 °C – 100 °C
Tcase0 °C – 83 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1310 (BGA)
Dimension34 mm x 28 mm
Ball Count1310
Ball CompSAC405
InterconnectBGA-1310

Atom C3558 is a 64-bit quad-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3558, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.2 GHz with a TDP of 16 W. The C3558 supports up to 256 GiB of dual-channel DDR4-1866 ECC memory. This model is part of Denverton's Network and Enterprise Storage SKUs and come with integrated QuickAssist Technology.

Cache[edit]

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$224 KiB
229,376 B
0.219 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L1D$96 KiB
98,304 B
0.0938 MiB
4x24 KiB6-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-1866
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels2
Max Bandwidth27.82 GiB/s
28,487.68 MiB/s
29.871 GB/s
29,871.498 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.82 GiB/s

Expansions[edit]

This chip incorporates 12 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 12
Configuration: x8, x4, x2, x1
USBRevision: 3.0
Max Ports: 8
SATARevision: 3.0
Max Ports: 12
HSIOMax Lanes: 12


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
2.5GbEYes (Ports: 2)
10GbEYes (Ports: 2)

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/c3558&oldid=93391"
Facts about "Atom C3558 - Intel"
RDF feed
l1$ size224 KiB (229,376 B, 0.219 MiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +