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{{renesas title|R-Car V2H}} | {{renesas title|R-Car V2H}} | ||
− | {{ | + | {{chip |
+ | |name=R-Car V2H | ||
+ | |image=r-car v2h.jpg | ||
+ | |designer=Renesas | ||
+ | |designer 2=ARM Holdings | ||
+ | |manufacturer=TSMC | ||
+ | |model number=V2H | ||
+ | |part number=R8A7792 | ||
+ | |market=Embedded | ||
+ | |first announced=August 28, 2014 | ||
+ | |first launched=October, 2016 | ||
+ | |family=R-Car | ||
+ | |series=2nd Gen | ||
+ | |frequency=1,000 MHz | ||
+ | |isa=ARMv8 | ||
+ | |isa family=ARM | ||
+ | |microarch=Cortex-A15 | ||
+ | |core name=Cortex-A15 | ||
+ | |process=28 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=2 | ||
+ | |thread count=2 | ||
+ | |max cpus=1 | ||
+ | |v core=1.03 V | ||
+ | |v io=3.3 V | ||
+ | |package module 1={{packages/renesas/fcbga-64}} | ||
+ | }} | ||
'''R-Car V2H''' is high-performance embedded {{arch|64}} [[dual-core]] [[arm]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2014. The V2H has two {{armh|Cortex-A15}} cores operating at 1 GHz and incorporates the [[imagination technologies|Imagination]] {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to DDR3-1600 memory. | '''R-Car V2H''' is high-performance embedded {{arch|64}} [[dual-core]] [[arm]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2014. The V2H has two {{armh|Cortex-A15}} cores operating at 1 GHz and incorporates the [[imagination technologies|Imagination]] {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to DDR3-1600 memory. | ||
+ | |||
+ | Samples for the V2H were available starting September 2014 with Renesas expecting mass production to begin around October 2016 with combined production reaching a volume of 500,000 units per month by October 2017. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|l1=Cortex-A15 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=2x32 KiB | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l2 cache=1 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-1600 | ||
+ | |ecc=Yes | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=32 bit | ||
+ | |max bandwidth=5.96 GiB/s | ||
+ | |bandwidth schan=5.96 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | * Flash ROM and SRAM Data bus width: 8/16 bit | ||
+ | * CAN 2 channels | ||
+ | * Ethernet AVB; 1000 Mbps, 100 Mbps, IEEE802.3 PHY | ||
+ | |||
+ | == Graphics == | ||
+ | {{integrated graphics | ||
+ | | gpu = PowerVR SGX531 | ||
+ | | designer = Imagination Technologies | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{arm features | ||
+ | |thumb=No | ||
+ | |thumb2=No | ||
+ | |thumbee=No | ||
+ | |vfpv1=No | ||
+ | |vfpv2=No | ||
+ | |vfpv3=No | ||
+ | |vfpv3-d16=No | ||
+ | |vfpv3-f16=No | ||
+ | |vfpv4=Yes | ||
+ | |vfpv4-d16=No | ||
+ | |vfpv5=No | ||
+ | |neon=Yes | ||
+ | |trustzone=Yes | ||
+ | |jazelle=No | ||
+ | |wmmx=No | ||
+ | |wmmx2=No | ||
+ | }} | ||
+ | |||
+ | == Block Diagram == | ||
+ | ::[[File:blk rcar v2h.jpg|700px]] | ||
+ | |||
+ | == Development Board ("BLANCHE") == | ||
+ | * 210 mm x 160 mm | ||
+ | * R-Car V2H | ||
+ | * 64 MiB NOR & 4 MiB SPI flash memory | ||
+ | * 1 GB DDR3-DRAM-1600; 32-bit configuration | ||
+ | * 6 x video inputs | ||
+ | * EtherAVB (GMII/MII) | ||
+ | * SD card host interfaces | ||
+ | * Two CAN interfaces | ||
+ | * HDMI and RGB display-out | ||
+ | * switches, LEDs, I/O expansion headers | ||
+ | * JTAG debug/trace connectors | ||
+ | * expansion connectors | ||
+ | * Five-channel low-delay H.264/JPEG decoder | ||
+ | * Image recognition engines |
Latest revision as of 15:32, 13 December 2017
Edit Values | |||||||||||
R-Car V2H | |||||||||||
General Info | |||||||||||
Designer | Renesas, ARM Holdings | ||||||||||
Manufacturer | TSMC | ||||||||||
Model Number | V2H | ||||||||||
Part Number | R8A7792 | ||||||||||
Market | Embedded | ||||||||||
Introduction | August 28, 2014 (announced) October, 2016 (launched) | ||||||||||
General Specs | |||||||||||
Family | R-Car | ||||||||||
Series | 2nd Gen | ||||||||||
Frequency | 1,000 MHz | ||||||||||
Microarchitecture | |||||||||||
ISA | ARMv8 (ARM) | ||||||||||
Microarchitecture | Cortex-A15 | ||||||||||
Core Name | Cortex-A15 | ||||||||||
Process | 28 nm | ||||||||||
Technology | CMOS | ||||||||||
Word Size | 64 bit | ||||||||||
Cores | 2 | ||||||||||
Threads | 2 | ||||||||||
Multiprocessing | |||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||
Electrical | |||||||||||
Vcore | 1.03 V | ||||||||||
VI/O | 3.3 V | ||||||||||
Packaging | |||||||||||
|
R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.
Samples for the V2H were available starting September 2014 with Renesas expecting mass production to begin around October 2016 with combined production reaching a volume of 500,000 units per month by October 2017.
Contents
Cache[edit]
- Main article: Cortex-A15 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
- Flash ROM and SRAM Data bus width: 8/16 bit
- CAN 2 channels
- Ethernet AVB; 1000 Mbps, 100 Mbps, IEEE802.3 PHY
Graphics[edit]
Integrated Graphics Information
|
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Features[edit]
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Block Diagram[edit]
Development Board ("BLANCHE")[edit]
- 210 mm x 160 mm
- R-Car V2H
- 64 MiB NOR & 4 MiB SPI flash memory
- 1 GB DDR3-DRAM-1600; 32-bit configuration
- 6 x video inputs
- EtherAVB (GMII/MII)
- SD card host interfaces
- Two CAN interfaces
- HDMI and RGB display-out
- switches, LEDs, I/O expansion headers
- JTAG debug/trace connectors
- expansion connectors
- Five-channel low-delay H.264/JPEG decoder
- Image recognition engines
Facts about "R-Car V2H - Renesas"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car V2H - Renesas#package + |
base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
core count | 2 + |
core name | Cortex-A15 + |
core voltage | 1.03 V (10.3 dV, 103 cV, 1,030 mV) + |
designer | Renesas + and ARM Holdings + |
family | R-Car + |
first announced | August 28, 2014 + |
first launched | October 2016 + |
full page name | renesas/r-car/v2h + |
has ecc memory support | true + |
instance of | microprocessor + |
integrated gpu | PowerVR SGX531 + |
integrated gpu designer | Imagination Technologies + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | October 2016 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
max memory channels | 1 + |
microarchitecture | Cortex-A15 + |
model number | V2H + |
name | R-Car V2H + |
package | FCBGA-64 + |
part number | R8A7792 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
series | 2nd Gen + |
smp max ways | 1 + |
supported memory type | DDR3-1600 + |
technology | CMOS + |
thread count | 2 + |
word size | 64 bit (8 octets, 16 nibbles) + |