Latest revision as of 15:32, 13 December 2017

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R-Car H2
General Info
Designer	Renesas, ARM Holdings
Manufacturer	TSMC
Model Number	H2
Part Number	R8A7790
Market	Embedded
Introduction	March 25, 2013 (announced) June, 2014 (launched)
General Specs
Family	R-Car
Series	2nd Gen
Frequency	1,500 MHz, 1,000 MHz, 780 MHz
Microarchitecture
ISA	ARMv7 (ARM), SuperH (SuperH)
Microarchitecture	Cortex A15, Cortex A7, SH-4A
Core Name	Cortex A15, Cortex A7, SH-4A
Process	28 nm
Technology	CMOS
Word Size	32 bit
Cores	9
Threads	9
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.0 V
VI/O	3.3, 1.8
Packaging
Package FCBGA-831 (BGA) Dimension 27 mm x 27 mm Pitch 0.80 mm Ball Count 831 Interconnect BGA-831

R-Car H2 is a high-end embedded nona-core SoC for the automotive industry introduced by Renesas in early 2013. The H2 incorporates four Cortex-A15 cores operating at 1.5 GHz, four Cortex-A7 cores operating at 1 GHz, and one SH-4A core operating at 780 MHz for real-time processing. This SoC incorporates Imagination's PowerVR G6400 GPU operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.

Cache[edit]

Main articles: Cortex-A15 § Cache and Cortex-A7 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 576 KiB 589,824 B 0.563 MiB L1I$ 288 KiB 294,912 B 0.281 MiB 9x32 KiB     L1D$ 288 KiB 294,912 B 0.281 MiB 9x32 KiB     L2$ 2.5 MiB 2,560 KiB 2,621,440 B 0.00244 GiB

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1600 Supports ECC No Controllers 1 Channels 2 Width 32 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 5.96 GiB/s Double 11.92 GiB/s

Expansions[edit]

• Flash ROM and SRAM, Data bus width: 8 or 16 bits
• PCI Express2.0 (1 lane)
• USB 3.0 Host interface × 1 port (wPHY)
• USB 2.0 Host interface × 3 port (wPHY)
• SD Host interface × 4 ch (SDXC, UHS-I)
• Multimedia card interface × 2 ch
• Serial ATA interface × 2 ch
• I²C bus interface × 8 ch
• Serial communication interface (SCIF) × 10 ch
• Quad serial peripheral interface (QSPI) × 1 ch (for boot)
• Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
• Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics[edit]

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR G6400 Designer Imagination Technologies Execution Units 1 Max Displays 2 Frequency 550 MHz 0.55 GHz 550,000 KHz

Features[edit]

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv4 Vector Floating Point (VFP) v4 Extension NEON Advanced SIMD extension

Block Diagram[edit]

Dev Board ("LAGER")[edit]

• 210 mm x 180 mm
• R-Car H2
• 68 MiB serial flash memory
• 4 GiB DDR3-DRAM-1600; 1x 64-bit configuration
• RS-232C, UART, USB, SD, LAN, SATA, PCIe , CAN and MLB interfaces (partially via connector)
• HDMI and LVDS display-out
• switches, LEDs, I/O expansion header