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Difference between revisions of "renesas/r-car/m1a"
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{{renesas title|R-Car M1A}}
 
{{renesas title|R-Car M1A}}
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{{chip
 
|name=R-Car M1A
 
|name=R-Car M1A
 
|no image=Yes
 
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|first announced=February 16, 2011
 
|first announced=February 16, 2011
 
|first launched=June, 2012
 
|first launched=June, 2012
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|release price=$75
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|release price=$70
 
|family=R-Car
 
|family=R-Car
 
|series=1st Gen
 
|series=1st Gen
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|package module 1={{packages/renesas/fcbga-472}}
 
|package module 1={{packages/renesas/fcbga-472}}
 
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'''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.
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'''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX540}} [[GPU]] operating at 200 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.
  
 +
Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.
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== Cache ==
 
== Cache ==
 
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
 
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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|wmmx2=No
 
|wmmx2=No
 
}}
 
}}
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== Block Diagram ==
 +
: [[File:rcar m1a block.png|650px]]
 +
 +
 +
: [[File:r-car m1a block.png|650px]]
 +
 +
== Dev Board ("MILAN") ==
 +
* 165 mm x 120 mm
 +
* R-Car M1A
 +
* 64 MiB flash memory
 +
* 512 MiB DDR3-DRAM
 +
* RS-232C, UART, USB,SD, LAN, CAN, MLB interfaces
 +
* HDMI display out (with HDMI to DVI adapter)
 +
* switches, LEDs,I/O expansion headers
 +
 +
 +
: [[File:renesas milan m1a board.png|450px]]

Latest revision as of 15:32, 13 December 2017

Edit Values
R-Car M1A
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberM1A
Part NumberR8A77781
MarketEmbedded
IntroductionFebruary 16, 2011 (announced)
June, 2012 (launched)
Release Price$70
General Specs
FamilyR-Car
Series1st Gen
Frequency800 MHz
Microarchitecture
ISAARMv7 (ARM), SuperH (SuperH)
MicroarchitectureCortex-A9, SH-4A
Core NameCortex-A9, SH-4A
Process40 nm
TechnologyCMOS
Word Size32 bit
Cores2
Threads2
Max Memory1 GiB
Electrical
Vcore1.2 V
VI/O3.3 V
Packaging
PackageFCBGA-472 (BGA)
Dimension21 mm x 21 mm
Pitch0.80 mm
Ball Count472
InterconnectBGA-472

R-Car M1A is a mid-range performance embedded dual-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1A features a single Cortex-A9 core and an additional SH-4A core, both operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.

Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.

Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-800
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth7.95 GiB/s
8,140.8 MiB/s
8.536 GB/s
8,536.248 MB/s
0.00776 TiB/s
0.00854 TB/s
Bandwidth
Single 3.97 GiB/s
Double 7.95 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4
GP I/OYes
JTAGYes
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 3 x SD

Graphics[edit]

  • 20MPoly/s; 1000MPix/s; 3.2GFlops/s

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX540
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency200 MHz
0.2 GHz
200,000 KHz
Standards
OpenGL2.1
OpenGL ES2.0

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv3Vector Floating Point (VFP) v3 Extension
NEONAdvanced SIMD extension
JazelleDirect Bytecode eXecution


Block Diagram[edit]

rcar m1a block.png


r-car m1a block.png

Dev Board ("MILAN")[edit]

  • 165 mm x 120 mm
  • R-Car M1A
  • 64 MiB flash memory
  • 512 MiB DDR3-DRAM
  • RS-232C, UART, USB,SD, LAN, CAN, MLB interfaces
  • HDMI display out (with HDMI to DVI adapter)
  • switches, LEDs,I/O expansion headers


renesas milan m1a board.png
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/m1a&oldid=71196"
Facts about "R-Car M1A - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car M1A - Renesas#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +
core count2 +
core nameCortex-A9 + and SH-4A +
core voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedFebruary 16, 2011 +
first launchedJune 2012 +
full page namerenesas/r-car/m1a +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units2 +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 + and SuperH +
isa familyARM + and SuperH +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
ldateJune 2012 +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) +
max memory channels2 +
microarchitectureCortex-A9 + and SH-4A +
model numberM1A +
nameR-Car M1A +
packageFCBGA-472 +
part numberR8A77781 +
process40 nm (0.04 μm, 4.0e-5 mm) +
release price$ 70.00 (€ 63.00, £ 56.70, ¥ 7,233.10) +
series1st Gen +
supported memory typeDDR3-1066 + and DDR2-800 +
technologyCMOS +
thread count2 +
word size32 bit (4 octets, 8 nibbles) +