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Latest revision as of 13:17, 16 July 2017

Summary[edit]

Intel Skylake SP 4-way SMP 3 UPI links. My own drawing.

Licensing[edit]

Permission is given by the author to use the artwork on WikiChip only and for WikiChip publication only. Any use by anyone except WikiChip constitutes copyright infringement.

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Date/TimeThumbnailDimensionsUserComment
current13:17, 16 July 2017Thumbnail for version as of 13:17, 16 July 20171,389 × 714 (437 KB)At32Hz (talk | contribs)
00:25, 15 July 2017Thumbnail for version as of 00:25, 15 July 20171,389 × 714 (436 KB)At32Hz (talk | contribs)corrected mems more accurately
04:53, 14 July 2017Thumbnail for version as of 04:53, 14 July 20171,164 × 714 (278 KB)At32Hz (talk | contribs)Intel {{intel|Skylake SP|l=core}} 4-way SMP 3 UPI links. My own drawing.
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