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Difference between revisions of "intel/xeon e3/e3-1240 v5"
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{{intel title|Xeon E3-1240 v5}} | {{intel title|Xeon E3-1240 v5}} | ||
− | {{ | + | {{chip |
|name=Xeon E3-1240 v5 | |name=Xeon E3-1240 v5 | ||
|image=skylake dt (front).png | |image=skylake dt (front).png | ||
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|first announced=October 19, 2015 | |first announced=October 19, 2015 | ||
|first launched=October 19, 2015 | |first launched=October 19, 2015 | ||
+ | |last order=October 26, 2018 | ||
+ | |last shipment=April 12, 2019 | ||
|release price=$282 | |release price=$282 | ||
|family=Xeon E3 | |family=Xeon E3 | ||
Line 19: | Line 21: | ||
|frequency=3,500 MHz | |frequency=3,500 MHz | ||
|turbo frequency1=3,900 MHz | |turbo frequency1=3,900 MHz | ||
+ | |turbo frequency=Yes | ||
|bus type=DMI 3.0 | |bus type=DMI 3.0 | ||
|bus links=4 | |bus links=4 | ||
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|tstorage max=125 °C | |tstorage max=125 °C | ||
|package module 1={{packages/intel/lga-1151}} | |package module 1={{packages/intel/lga-1151}} | ||
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}} | }} | ||
'''Xeon E3-1240 v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]. | '''Xeon E3-1240 v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]. |
Latest revision as of 23:29, 6 April 2018
Edit Values | ||||||||||||
Xeon E3-1240 v5 | ||||||||||||
General Info | ||||||||||||
Designer | Intel | |||||||||||
Manufacturer | Intel | |||||||||||
Model Number | E3-1240 v5 | |||||||||||
Part Number | CM8066201921715, BX80662E31240V5 | |||||||||||
S-Spec | SR2CM, SR2LD | |||||||||||
Market | Server | |||||||||||
Introduction | October 19, 2015 (announced) October 19, 2015 (launched) | |||||||||||
End-of-life | October 26, 2018 (last order) April 12, 2019 (last shipment) | |||||||||||
Release Price | $282 | |||||||||||
Shop | Amazon | |||||||||||
General Specs | ||||||||||||
Family | Xeon E3 | |||||||||||
Series | E3-1200 v5 | |||||||||||
Locked | Yes | |||||||||||
Frequency | 3,500 MHz | |||||||||||
Turbo Frequency | Yes | |||||||||||
Turbo Frequency | 3,900 MHz (1 core) | |||||||||||
Bus type | DMI 3.0 | |||||||||||
Bus rate | 4 × 8 GT/s | |||||||||||
Clock multiplier | 35 | |||||||||||
CPUID | 506E3 | |||||||||||
Microarchitecture | ||||||||||||
ISA | x86-64 (x86) | |||||||||||
Microarchitecture | Skylake | |||||||||||
Platform | Greenlow | |||||||||||
Chipset | Sunrise Point | |||||||||||
Core Name | Skylake DT | |||||||||||
Core Family | 6 | |||||||||||
Core Model | 94 | |||||||||||
Core Stepping | R0 | |||||||||||
Process | 14 nm | |||||||||||
Technology | CMOS | |||||||||||
Die | 122 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 4 | |||||||||||
Threads | 8 | |||||||||||
Max Memory | 64 GiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||||
Electrical | ||||||||||||
Vcore | 0.55 V-1.52 V | |||||||||||
TDP | 80 W | |||||||||||
Tjunction | 0 °C – 100 °C | |||||||||||
Tstorage | -25 °C – 125 °C | |||||||||||
Packaging | ||||||||||||
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Xeon E3-1240 v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
This chip has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1240 v5 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1240 v5 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3L-1600 + and DDR4-2133 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |