Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e3/e3-1240l v5"
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Latest revision as of 15:26, 13 December 2017
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| Xeon E3-1240L v5 | ||||||||||||
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| General Info | ||||||||||||
| Designer | Intel | |||||||||||
| Manufacturer | Intel | |||||||||||
| Model Number | E3-1240L v5 | |||||||||||
| Part Number | CM8066201935808 | |||||||||||
| S-Spec | SR2CW, SR2LN | |||||||||||
| Market | Server | |||||||||||
| Introduction | October 19, 2015 (announced) October 19, 2015 (launched) | |||||||||||
| Release Price | $278 | |||||||||||
| Shop | Amazon | |||||||||||
| General Specs | ||||||||||||
| Family | Xeon E3 | |||||||||||
| Series | E3-1200 v5 | |||||||||||
| Locked | Yes | |||||||||||
| Frequency | 2,100 MHz | |||||||||||
| Turbo Frequency | Yes | |||||||||||
| Turbo Frequency | 3,200 MHz (1 core) | |||||||||||
| Bus type | DMI 3.0 | |||||||||||
| Bus rate | 4 × 8 GT/s | |||||||||||
| Clock multiplier | 21 | |||||||||||
| CPUID | 506E3 | |||||||||||
| Microarchitecture | ||||||||||||
| ISA | x86-64 (x86) | |||||||||||
| Microarchitecture | Skylake | |||||||||||
| Platform | Greenlow | |||||||||||
| Chipset | Sunrise Point | |||||||||||
| Core Name | Skylake DT | |||||||||||
| Core Family | 6 | |||||||||||
| Core Model | 94 | |||||||||||
| Core Stepping | R0 | |||||||||||
| Process | 14 nm | |||||||||||
| Technology | CMOS | |||||||||||
| Die | 122 mm² | |||||||||||
| Word Size | 64 bit | |||||||||||
| Cores | 4 | |||||||||||
| Threads | 8 | |||||||||||
| Max Memory | 64 GiB | |||||||||||
| Multiprocessing | ||||||||||||
| Max SMP | 1-Way (Uniprocessor) | |||||||||||
| Electrical | ||||||||||||
| Vcore | 0.55 V-1.52 V | |||||||||||
| TDP | 25 W | |||||||||||
| Tjunction | 0 °C – 100 °C | |||||||||||
| Tstorage | -25 °C – 125 °C | |||||||||||
| Packaging | ||||||||||||
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Xeon E3-1240L v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 2.1 GHz with turbo boost of 3.2 GHz. The E3-1240L v5 has a TDP of 25 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.
Cache[edit]
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Graphics[edit]
This chip has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1240L v5 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1240L v5 - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Software Guard Extensions + and Secure Key Technology + |
| has intel enhanced speedstep technology | true + |
| has intel secure key technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3L-1600 + and DDR4-2133 + |
| x86/has software guard extensions | true + |