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Difference between revisions of "intel/xeon e3/e3-1565l v5"
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+ | '''Xeon E3-1565L v5''' is a {{arch|64}} [[quad-core]] [[x86]] high-end performance mobile workstation [[microprocessor]] introduced by [[Intel]] in early 2016. The E3-1565L v5, which is based on the {{intel|Skylake|l=arch}} microarchitecture and is fabricated on a [[14 nm process]], has a base frequency of 2.5 GHz and a {{intel|turbo boost}} frequency of up to 3.5 GHz with a TDP of 35 W. This processor incorporates the {{intel|Iris Pro Graphics 580}} [[integrated graphics]] operating at 350 MHz with a turbo frequency of 1.05 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory. | ||
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== Cache == | == Cache == | ||
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
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|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | |l4 cache=128 MiB | ||
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|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
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Latest revision as of 15:27, 13 December 2017
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Xeon E3-1565L v5 | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | E3-1565L v5 | ||||||||||||
S-Spec | SR2R8 | ||||||||||||
Market | Server | ||||||||||||
Introduction | May 31, 2016 (announced) May 31, 2016 (launched) | ||||||||||||
Release Price | $417.00 | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Xeon E3 | ||||||||||||
Series | E3-1500 v5 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 2,500 MHz | ||||||||||||
Turbo Frequency | 3,500 MHz (1 core) | ||||||||||||
Bus type | DMI 3.0 | ||||||||||||
Bus rate | 4 × 8 GT/s | ||||||||||||
Clock multiplier | 25 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Skylake | ||||||||||||
Core Name | Skylake H | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 94 | ||||||||||||
Core Stepping | N0 | ||||||||||||
Process | 14 nm | ||||||||||||
Technology | CMOS | ||||||||||||
MCP | Yes (2 dies) | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 4 | ||||||||||||
Threads | 8 | ||||||||||||
Max Memory | 64 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.55 V-1.52 V | ||||||||||||
TDP | 35 W | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
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Xeon E3-1565L v5 is a 64-bit quad-core x86 high-end performance mobile workstation microprocessor introduced by Intel in early 2016. The E3-1565L v5, which is based on the Skylake microarchitecture and is fabricated on a 14 nm process, has a base frequency of 2.5 GHz and a turbo boost frequency of up to 3.5 GHz with a TDP of 35 W. This processor incorporates the Iris Pro Graphics 580 integrated graphics operating at 350 MHz with a turbo frequency of 1.05 GHz and incorporating 128 MiB of eDRAM on-package. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
This integrated graphics includes an additional 128 MiB of eDRAM on-chip.
Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1565L v5 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1565L v5 - Intel#io + |
device id | 0x193D + |
has ecc memory support | true + |
integrated gpu | Iris Pro Graphics P580 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 72 + |
integrated gpu max frequency | 1,050 MHz (1.05 GHz, 1,050,000 KHz) + |
integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |