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Difference between revisions of "intel/core i7/i7-6500u"
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{{intel title|Core i7-6500U}} | {{intel title|Core i7-6500U}} | ||
− | {{ | + | {{chip |
|name=Core i7-6500U | |name=Core i7-6500U | ||
− | |image=skylake ( | + | |image=skylake u (front; standard).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=i7-6500U | |model number=i7-6500U | ||
+ | |part number=FJ8066201930408 | ||
|s-spec=SR2EZ | |s-spec=SR2EZ | ||
|market=Mobile | |market=Mobile | ||
− | |family=Core | + | |first announced=September 1, 2015 |
− | |series= | + | |first launched=September 27, 2015 |
+ | |release price=$393 | ||
+ | |family=Core i7 | ||
+ | |series=i7-6000 | ||
|locked=Yes | |locked=Yes | ||
|frequency=2,500 MHz | |frequency=2,500 MHz | ||
|turbo frequency1=3,100 MHz | |turbo frequency1=3,100 MHz | ||
+ | |turbo frequency2=3,000 MHz | ||
|bus type=OPI | |bus type=OPI | ||
|bus rate=4 GT/s | |bus rate=4 GT/s | ||
Line 49: | Line 54: | ||
|package module 1={{packages/intel/fcbga-1356}} | |package module 1={{packages/intel/fcbga-1356}} | ||
}} | }} | ||
− | '''Core i7-6500U''' is a {{arch|64}} [[dual-core]] high-end performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.5 GHz with a {{intel|turbo boost}} of up to 3.1 GHz. The i7-6500U has a TDP of 15 W with a configurable-down | + | '''Core i7-6500U''' is a {{arch|64}} [[dual-core]] high-end performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.5 GHz with a {{intel|turbo boost}} of up to 3.1 GHz. The i7-6500U has a TDP of 15 W with a configurable TDP-down of 7.5 W (800 MHz) and a configurable TDP-up of 25 W (2.6 GHz). This chip incorporates the {{intel|HD Graphics 520}} GPU operating at 300 MHz with a burst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. |
== Cache == | == Cache == | ||
Line 162: | Line 167: | ||
|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | + | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No |
Latest revision as of 15:22, 13 December 2017
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Core i7-6500U | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | i7-6500U | ||||||||||||
Part Number | FJ8066201930408 | ||||||||||||
S-Spec | SR2EZ | ||||||||||||
Market | Mobile | ||||||||||||
Introduction | September 1, 2015 (announced) September 27, 2015 (launched) | ||||||||||||
Release Price | $393 | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Core i7 | ||||||||||||
Series | i7-6000 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 2,500 MHz | ||||||||||||
Turbo Frequency | 3,100 MHz (1 core), 3,000 MHz (2 cores) | ||||||||||||
Bus type | OPI | ||||||||||||
Bus rate | 4 GT/s | ||||||||||||
Clock multiplier | 25 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Skylake | ||||||||||||
Core Name | Skylake U | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 78 | ||||||||||||
Core Stepping | D1 | ||||||||||||
Process | 14 nm | ||||||||||||
Transistors | 1,750,000,000 | ||||||||||||
Technology | CMOS | ||||||||||||
Die | 98.57 mm² 10.3 mm × 9.57 mm | ||||||||||||
MCP | Yes (2 dies) | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 2 | ||||||||||||
Threads | 4 | ||||||||||||
Max Memory | 32 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.55 V-1.52 V | ||||||||||||
TDP | 15 W | ||||||||||||
cTDP down | 7.5 W | ||||||||||||
cTDP down frequency | 800 MHz | ||||||||||||
cTDP up | 25 W | ||||||||||||
cTDP up frequency | 2,600 MHz | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
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Core i7-6500U is a 64-bit dual-core high-end performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.5 GHz with a turbo boost of up to 3.1 GHz. The i7-6500U has a TDP of 15 W with a configurable TDP-down of 7.5 W (800 MHz) and a configurable TDP-up of 25 W (2.6 GHz). This chip incorporates the HD Graphics 520 GPU operating at 300 MHz with a burst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Facts about "Core i7-6500U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-6500U - Intel#io + |
device id | 0x1916 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel identity protection technology support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel supervisor mode execution protection | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
integrated gpu | HD Graphics 520 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,050 MHz (1.05 GHz, 1,050,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 12 + |
supported memory type | DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |